Low-Power Integrated Circuit for Orientation Independent Acquisitions from Smart Accelerometers

Vita, Antonio De; Licciardo, Gian Domenico; Femia, Aldo; Benedetto, Luigi Di; Rubino, Alfredo; Pau, Danilo

doi:10.1007/978-3-030-37558-4_6

Cited by 2 publications

(1 citation statement)

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“…In addition, in HAR systems, inertial sensors can have an arbitrary and changeable orientation in space, with the gravity acceleration providing a variable contribution to each sample, which is related to the reference frame integral to the sensor. As the orientation of the sensor is generally unknown, this contribution needs some specific signal processing techniques to be removed [8]. In this context, the delay of the data transfer and the availability of connections make cloud unusable when real-time operation is required [9], let alone when privacy is at stake.…”

Section: Introductionmentioning

confidence: 99%

Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems

Vita

Pau

Benedetto

et al. 2020

2020 23rd Euromicro Conference on Digital System Design (DSD)

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Human Activity Recognition requires very high accuracy to be effectively employed into practical applications, ranging from elderly care to microsurgical devices. The highest accuracies are achieved by Deep Learning models, but these are not easily deployable in handheld or wearable devices with very constrained resources. We therefore present a new HAR system suitable for a compact FPGA implementation. A new Binarized Neural Network (BNN) architecture achieves the classification based on data from a single tri-axial accelerometer. From our experiments, the effect of gravity and the unknown orientation of the sensor cause a degradation of the accuracy. In order to compensate for these issues, we propose a HW-friendly algorithm to pre-process the raw acceleration signal. Moreover, the very low power and hardware friendly BNN has been trained and validated on the PAMAP2 dataset, for which the pre-processing operations increase the accuracy from 51% to 99% in the best case. Aiming for a low-power design, we designed both a custom circuit to perform the pre-processing operations and a hardware accelerator for the BNN. The design on FPGA features a power dissipation of 72 mW and occupies 6788 LUTs.

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Section: Introductionmentioning

confidence: 99%