PtSi source/drain p-type metal–oxide–semiconductor field-effect transistors (MOSFETs) have been fabricated at sub-40 nm channel lengths with 19 Å gate oxide. These devices employ gate-induced field emission through the PtSi ∼0.2 eV hole barrier to achieve current drives of ∼350 μA/μm at 1.2 V supply. Delay times estimated by the CV/I metric extend scaling trends of conventional p-MOSFETs to ∼2 ps. Thermal emission limits on/off current ratios to ∼20–50 in undoped devices at 300 K, while ratios of ∼107 are measured at 77 K. Off-state leakage can be reduced by implanting a thin layer of fully depleted donors beneath the active region to augment the Schottky barrier height or by use of ultrathin silicon-on-insulator substrates.
In this article we investigate the subthreshold behavior of PtSi source/drain Schottky barrier metal–oxide–semiconductor field-effect transistors. We demonstrate very large on/off ratios on bulk silicon devices and show that slight process variations can result in anomalous leakage paths that degrade the subthreshold swing and complicate investigations of device scaling.
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