With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essen- IntroductionA critical concern for embedded systems is the need to deliver high levels of performance given ever-diminishing power budgets. This is evident in the evolution of the mobile phone: in the last 7 years mobile phones have shown a 50X improvement in talk-time per gram of battery 1 , while at the same time taking on new computational tasks that only recently appeared on desktop computers, such as 3D graphics, audio/video, internet access, and gaming. As the breadth of applications for these devices widens, a single operating point is no longer sufficient to efficiently meet their processing and power consumption requirements. For example, MPEG video playback requires an order-of-magnitude higher performance than playing MP3s. However, running at the performance level necessary for video is energy-inefficient for audio. The gap between high performance and low power can be bridged through the use of dynamic voltage scaling (DVS) [16], where periods of low processor utilization are exploited by lowering the clock frequency to the minimum required level, allowing corresponding reduction in the supply voltage. Since dynamic energy scales quadratically with supply voltage, significant reduction in energy use can be obtained [14].Enabling systems to run at multiple frequency and voltage levels is a challenging process and requires characterization of the processor to ensure that its operation remains correct at the required operating points. The minimum possible supply voltage that results in correct operation is referred to as the critical supply voltage. The critical supply voltage must be sufficient to ensure correct operation in the face of a number of environmental and process related variabilities that can impact circuit performance. These include unexpected voltage drops in the power supply network, temperature fluctuations, gate-length and doping concentration variations, cross-coupling noise, etc. These variabilities may be data dependent, meaning that they exhibit their worst-case impact on circuit performance only under certain instruction and data sequences, and are composed of both local and global components. For instance, local process variations will impact specific regions of the die in different and independent ways, while global process variation impacts the circuit performance of the entire die and creates variation from one die to the next. Similarly, temperature and supply drop have local and global components, while cross-coupling noise is a predominantly local effect.To ensure correct operation under all possible variations, a conservative supply voltage is typically selected at designtime using corner analysis. Hence, margins are added ...
We have recently designed, fabricated, and successfully tested an experimental chip that validates a novel method for reducing clock dissipation through energy recovery. Our approach includes a singlephase sinusoidal clock signal, an L-C resonant sinusoidal clock generator, and an energy recovering flip-flop. Our chip comprises a dual-mode ASIC with two independent clock systems, one conventional and one energy recovering, and was fabricated in a 0.25µm bulk CMOS process. The ASIC computes a pipelined discrete wavelet transform with self-test and contains over 3500 gates. We have verified correct functionality and obtained power measurements in both modes of operation for frequencies up to 225MHz. In the energy recovering mode, our power measurements account for all of the dissipation factors, including the operation of the integrated resonant clock generator, and show a net energy savings over the conventional mode of operation. For example, at 115MHz, measured dissipation is between 60% and 75% of the conventional mode, depending on primary input activity. To our knowledge, this is the first ever published account of a direct experimentallymeasured comparison between a complete energy recovering ASIC chip and its conventional implementation correctly operating in silicon at frequencies exceeding 100MHz.
In this paper, we present the design and evaluation of a two-phase resonant clock generation and distribution system with layout-extracted inductor parameters in a 0.13µm copper process. The design includes a programmable replenishing clock generator and tunable capacitors that enable the exploration of skew, jitter, and clock amplitude. Our simulation results show that worst-case skew is within 8.5% of clock period in the range of 790MHz to 1.22GHz under a variety of load imbalance conditions. Furthermore, energy dissipation is at least 60% lower than conventional square waveform distribution.
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