Two-Phase Resonant Clock Distribution

Chueh, Juang-Ying; Papaefthymiou, Marios C.; Ziesler, C.H.

doi:10.1109/isvlsi.2005.74

Cited by 9 publications

(5 citation statements)

References 6 publications

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“…We have also performed post-layout simulations of a resonant clock tree spanning a 2mm-square area, focusing on the effect of clock skew and jitter due to static and dynamic load imbalance. Our simulations indicate a worst-case skew of 8.5% of the clock period at frequencies above 790MHz [5]. The skew tolerance of Boost Logic was therefore found to be sufficient for correct operation.…”

Section: Ghz-class Logicmentioning

confidence: 66%

Fast, efficient, recovering, and irreversible

Sathe

Chueh

Kim

et al. 2005

Proceedings of the 2nd Conference on Computing Frontiers

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Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at substantially lower power dissipation levels than their conventional counterparts. In this paper, we present two such chips that were designed in our research group and highlight some of the promising charge-recovery techniques in practice. Although their origins can be traced back to the early adiabatic circuits, these techniques approach energy recycling from a more practical angle, shedding reversibility to achieve operating frequencies in excess of 1GHz with relatively low overheads.

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Section: Ghz-class Logicmentioning

confidence: 66%

Fast, efficient, recovering, and irreversible

Sathe

Chueh

Kim

et al. 2005

Proceedings of the 2nd Conference on Computing Frontiers

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“…There have been versions of distributed LC-tank clocks demonstrated by industry on uniform Htrees [1,2] and clock grids [26] while academics have demonstrated prototypes of other clock topologies [8,40]. Several methodologies have been proposed to synthesize global H-tree resonant clocks [20], non-uniform global resonant clock trees [10], two-phase clocks [4,8], hierarchical local resonant clocks [5], and resonant clock grids using custom inductor sizing [18,19] and inductor-library-based sizing [17]. At least one company has a commercial product to support LC-tank resonant clocking [7, 26].…”

Section: Lc-tank Clocksmentioning

confidence: 99%

High-performance, low-power resonant clocking

Guthaus

Taşkın

2012

Proceedings of the International Conference on Computer-Aided Design

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Clock distribution networks consume a significant portion of onchip power. Traditional buffered clock distribution power is limited by frequency, capacitance, and activity rates. Resonant clock distributions can reduce this power by "recycling" energy on-chip and reducing the overall clock power. This tutorial introduces recent techniques for distributed-LC, traveling wave, and standing wave resonant clock distributions. In particular, the tutorial discusses the recent developments and open research problems. The tutorial covers both circuits, computer-aided design algorithms and methodologies for resonant clocking.

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“…Chueh et al [17] designed and evaluated a two-phase resonant clock generation and distribution system with layout extracted inductor parameters in a 0.13-m CMOS process. The circuit includes a programmable replenishing clock generator and tunable capacitors.…”

Section: Principle Of Quasi-resonant Interconnectsmentioning

confidence: 99%

Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology

Rosenfeld

Friedman

2009

IEEE Trans. VLSI Syst.

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Abstract-Design and analysis guidelines for quasi-resonant interconnect networks (QRN) are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of the on-chip interconnect and inductor to obtain both low power and low latency. Excellent agreement is shown between the proposed model and SpectraS simulations. The analysis and design of the inductor, insertion point, and driver resistance for minimum power-delay product is described. A case study demonstrates the design of a quasi-resonant interconnect, transmitting a 5 Gb/s data signal along a 5 mm line in a TSMC 0.18-m CMOS technology. As compared to classical repeater insertion, an average reduction of 91.1% and 37.8% is obtained in power consumption and delay, respectively. As compared to optical links, a reduction of 97.1% and 35.6% is observed in power consumption and delay, respectively.

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Two-Phase Resonant Clock Distribution

Cited by 9 publications

References 6 publications

Fast, efficient, recovering, and irreversible

Fast, efficient, recovering, and irreversible

High-performance, low-power resonant clocking

Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology

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