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With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essen- IntroductionA critical concern for embedded systems is the need to deliver high levels of performance given ever-diminishing power budgets. This is evident in the evolution of the mobile phone: in the last 7 years mobile phones have shown a 50X improvement in talk-time per gram of battery 1 , while at the same time taking on new computational tasks that only recently appeared on desktop computers, such as 3D graphics, audio/video, internet access, and gaming. As the breadth of applications for these devices widens, a single operating point is no longer sufficient to efficiently meet their processing and power consumption requirements. For example, MPEG video playback requires an order-of-magnitude higher performance than playing MP3s. However, running at the performance level necessary for video is energy-inefficient for audio. The gap between high performance and low power can be bridged through the use of dynamic voltage scaling (DVS) [16], where periods of low processor utilization are exploited by lowering the clock frequency to the minimum required level, allowing corresponding reduction in the supply voltage. Since dynamic energy scales quadratically with supply voltage, significant reduction in energy use can be obtained [14].Enabling systems to run at multiple frequency and voltage levels is a challenging process and requires characterization of the processor to ensure that its operation remains correct at the required operating points. The minimum possible supply voltage that results in correct operation is referred to as the critical supply voltage. The critical supply voltage must be sufficient to ensure correct operation in the face of a number of environmental and process related variabilities that can impact circuit performance. These include unexpected voltage drops in the power supply network, temperature fluctuations, gate-length and doping concentration variations, cross-coupling noise, etc. These variabilities may be data dependent, meaning that they exhibit their worst-case impact on circuit performance only under certain instruction and data sequences, and are composed of both local and global components. For instance, local process variations will impact specific regions of the die in different and independent ways, while global process variation impacts the circuit performance of the entire die and creates variation from one die to the next. Similarly, temperature and supply drop have local and global components, while cross-coupling noise is a predominantly local effect.To ensure correct operation under all possible variations, a conservative supply voltage is typically selected at designtime using corner analysis. Hence, margins are added ...

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An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of the scheduler can be improved by decreasing the number of tag comparisons necessary to schedule instructions. Using detailed simulation-based analyses, we find that most instructions enter the window with at least one of their input operands already available. By putting these instructions into specialized windows with fewer tag comparators, load capacitance on the scheduler critical path can be reduced, with only very small effects on program throughput. For instructions with multiple unavailable operands, we introduce a last-tag speculation mechanism that eliminates all remaining tag comparators except those for the last arriving input operand. By combining these two tag-reduction schemes, we are able to construct dynamic schedulers with approximately one quarter of the tag comparators found in conventional designs. Conservative circuit-level timing analyses indicate that the optimized designs are 20-45% faster and require 10-20% less power, depending on instruction window size.