Optical beam induced resistance change (OBIRCH) is one popular technique for isolating electrical shorts in process development test structures for 130nm and 110nm device technologies. However, OBIRCH inspection on 90nm technology is not always successful: since the OBIRCH signals of samples are very weak, or even comparable to noise. To overcome this, two alternative and complementary methods for isolating the failure have been developed. The first method is to calculate the coarse position of the defect directly from electrical resistance measurements. The second method is to enhance the OBIRCH signal using FIB circuit modification within the test structure. These methods can help locate defect at this structure by using electrical analysis only or enhancing the OBIRCH signal. The first method is an easy and quick method for short failure isolation, while the second can exactly locate the position of failure if the first method does not reveal a surface defect.
Modern semiconductor devices are continuing to be scaled down and the complexity of the processes involved in producing the devices keeps increasing, in conjunction with this, sample preparation and analysis are increasingly important for accurately determining the sources of defects and failure mechanisms in terms of process integration. This paper discusses ways to characterize integration-driven defects using deprocessing techniques and cross-section imaging to obtain 3-D views of such defects. As an example a single-via test structure is evaluated. The article focuses on the techniques used to deprocess the single-via structure using a combination of RIE, FIB, and wet etching to expose the single via while maintaining the integrity of the structure. The resulting 3-D view of the structure and associated defect allowed for improved understanding of the defect and its origin. This understanding enabled process optimization to minimize such defect formation.
With the advancement in technology and lower operating voltage, new standards have evolved in circuit layout and design. Some of these new standards have increased the difficulties of the physical failure analysis process, especially on the front-end. The phenomenon described in this paper is the unusual voltage contrast (VC) and conductive atomic force microscope (C-AFM) curve on a non-isolated active region. The model and mechanism are demonstrated for front-end failure analysis. Based on this, the solution for analysis is investigated.
A failure incurred in the front-end is typically a bottleneck to production due the need for physical failure analysis (PFA). Often the challenge is to perform timely localization of the front-end defect, or finding the exact physical defect for process improvement. Many process parameters affect the device behaviour and cause the front-end defect. Simply, the failures are of two types: high-resistance and leakage. A leakage mode defect is the most difficult to inspect. Although conductive atomic force microscopy and six probes nano-probing are popular tools for front-end failure inspection, some specific defects still need more effort. The electrical phenomenon and analysis of a crystalline defect will be demonstrated in this paper. The details will be discussed below.
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