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The IC test industry has struggled .for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrilxd properti'es. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and lest facilities and from public literature [l-601. We describe test pattern requirements for each defect class and propose a test paradigm.

Defects in CMOS ICs cause unique electrical characteristics. Digital CMOS ICs can perform their terminal logic functions in spite of significant imperfections such as open or short circuits. The effects of these commonly occurring defects must be understood to develop test strategies that minimize the escape of ICs with defects that either degrade reliability or compromise circuit performance. This paper summarizes and adds new information regarding electrical properties of CMOS IC defects. The parametric or logic measurements required to detect each type of defect in a production test environment are emphasized,

The electrical effects of CMOS IC physical defects that caused stuck-open faults are evaluated, including their voltage levels, quiescent power supply current (IDDQ), transient response, and important testing considerations. The transient responses of the defective node voltage and power supply current to the high impedance state caused by a stuck-open defect were measured to determine if the IDDQ measurement technique could detect stuck-open faults. technique does detect stuck-open faults in some designs, but detection is not guaranteed for all circuits. reduce the probability of stuck-open fault occurrence are presented.