CMOS IC stuck-open-fault electrical effects and design considerations

Soden, J.M.; Treece, R.K.; Taylor, Martin; Hawkins, C.F.

doi:10.1109/test.1989.82325

Cited by 90 publications

(32 citation statements)

References 14 publications

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“…Let us now observe the case when the average value is fixed and K is changed. In this case, when K=1, we obtain an exponential function as distinctly shown by Equation (2). As K is increased, it changes to a distribution with a peak at a location larger than 0.…”

Section: Detection Methods Using a Gamma Distribution Approximationmentioning

confidence: 70%

“…F(x)= k / (K)×x K-1 e -x (0=<x< ) Average X=K/ , Variance 2 =K/ 2 (2) The assumption of a gamma distribution is based on the following reasoning. First, if the average value X and K are determined, then is determined unconditionally.…”

Section: Detection Methods Using a Gamma Distribution Approximationmentioning

confidence: 99%

“…Such a method also logically produces higher quality in a shorter time. On the other hand, a IDDQ test has been initially devised in order to detect open (and floating gate) faults [1,2]. A large number of publications have later shown that this test is also effective for short faults, AC faults and stuck-at faults as well [3].…”

Section: Introductionmentioning

confidence: 99%

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IDDQ Testing Method using a Scan Pattern for Production Testing

Hirase

Goi

Tanaka

2005

14th Asian Test Symposium (ATS'05)

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With the miniaturization of the diffusion process, the leak current per transistor tends to increase and the number of transistors per die tends to become larger, thus rendering more difficult the discrimination through the absolute value of IDDQ (Quiescent power supply current) that is required to detect defects on VLSI (Very Large Scale Integration). On the other hand, scan patterns convenient for their logical quality improvement are widely used. When adopting such a scan pattern and measuring the IDDQ, one finds that the measured values do not fluctuate greatly. In this paper, we will present a method of determining good and defective dies by making an approximation of this distribution using a gamma distribution and we will demonstrate the efficiency of our method through corroborative results.

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Section: Detection Methods Using a Gamma Distribution Approximationmentioning

confidence: 70%

Section: Detection Methods Using a Gamma Distribution Approximationmentioning

confidence: 99%

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IDDQ Testing Method using a Scan Pattern for Production Testing

Hirase

Goi

Tanaka

2005

14th Asian Test Symposium (ATS'05)

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“…Since the SOF model was first proposed in [2], intensive research effort has been devoted to improving the characterization [3], testing [4]- [6], and diagnosis [9]- [12] of this class of faults. These studies have demonstrated its efficiency for a wide spectrum of technologies, including the deep submicrometer domain.…”

Section: Introductionmentioning

confidence: 99%

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Arumí

Rodríguez-Montañés

Figueras

2016

IEEE Trans. VLSI Syst.

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Abstract-Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.

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“…IDDQ testing has been shown to be an effective complement to standard stuck-at fault testing due to its ability to detect many of those defects that are not correctly modeled as stuck-at faults [6][7][8][9][10]. Moreover, elevated Iix~e has been shown to be a reliability hazard even when a device passes functional testing.…”

Section: Introductionmentioning

confidence: 99%

ITA: An algorithm for I DDQ testability analysis

McNamer

Nagle

1996

J Electron Test

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This paper presents the IDDQ Testability Analysis (ITA) algorithm for the estimation of a circuit design's leakage fault testability. The algorithm is based on the calculation of the probability of applying each of a set of "essential vectors" to each gate in the circuit. The essential vectors for each gate represent the minimal vector set that provides maximal leakage fault coverage.ITA assumes independence of circuit net values, except in the case of reconvergent fanout. Reconvergent fanout is identified by "levetizing" the circuit and propagating sets of labels from the primary inputs forward through the circuit, beginning with unique labels (integers) on each primary input. ITA evaluation of reconvergent fanout points then uses a backward implication procedure to calculate the essential vector probability values for the reconvergent gate, except in the case where backward implication is not deterministic.Results of an implementation of ITA are presented for a set of benchmark circuits, including a sample of the ISCAS '85 and ' 89 circuits.

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CMOS IC stuck-open-fault electrical effects and design considerations

Cited by 90 publications

References 14 publications

IDDQ Testing Method using a Scan Pattern for Production Testing

IDDQ Testing Method using a Scan Pattern for Production Testing

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

ITA: An algorithm for I DDQ testability analysis

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