Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Abstract

Abstract-Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.

Impact of Resistive Open Faults on Inverter Chain and 7t Sram

“…Integrated Circuit (IC) mean several number of transistors are interconnected with each other. Resistive open faults (ROFs) represents the degradation [1] [13] [14] in conductivity within a circuit's interconnects, due to inevitable manufacturing failures in both current and emerging technologies. Such type of faults mainly cause performance failures and reliability risks, whose magnitude is not only voltage-sensitive but also influenced by the electrical characteristics of the driving and driven CMOS networks.…”

Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure

“…10 An inverter with open defect on the drain of the PMOS transistor[44] However, in nanometer technologies the impact of transistor leakage currents and downstream parasitic capacitances including the line and load capacitances is nonnegligible. Their influence might increase the output voltage above the threshold of logic 0 in this case and result in a test escape.…”

“…Their influence might increase the output voltage above the threshold of logic 0 in this case and result in a test escape. The analysis of the capacitances, as the dominant factor, leads to obtaining the minimum line length that corresponds to the capacitances satisfying this condition[44].c) Layout levelDue to the complexity of modern ICs, the use of standard library cells has been increased in the circuit design. The traditional fault models used for test pattern generation are successful in representing the defects on the inputs and outputs of the cells as well as the interconnects.…”