The electrical effects of CMOS IC physical defects that caused stuck-open faults are evaluated, including their voltage levels, quiescent power supply current (IDDQ), transient response, and important testing considerations. The transient responses of the defective node voltage and power supply current to the high impedance state caused by a stuck-open defect were measured to determine if the IDDQ measurement technique could detect stuck-open faults. technique does detect stuck-open faults in some designs, but detection is not guaranteed for all circuits. reduce the probability of stuck-open fault occurrence are presented.
Many defects causing bridges, breaks, and transistor stuckons in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. These undetected, non-traditional faults may be detected as increased propagation time or as excessive quiescent power supply current (IDDQ). In this paper we compare the cost of testing for excess IDDQ caused by bridge, break and transistors stuck-on faults versus the cost of traditional testing methods.
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