Defect-based delay testing of resistive vias-contacts a critical evaluation

Baker, K.; Gronthoud, G.; Lousberg, M.; Schanstra, I.; Hawkins, C.F.

doi:10.1109/test.1999.805769

Cited by 112 publications

(53 citation statements)

References 12 publications

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“…The first one collects all the principal information divided in four classes: [16], whose blif representation is shown in figure 5. 3.…”

Section: Methodsmentioning

confidence: 99%

“…However, the approach was specifically applied to the case of small combinational modules whose timing can be reasonably modeled using the timing arc delay model [17]. The use of such an approximate model is justified by the growing relevance of interconnect delays in submicron digital ICs [27] and by the relevant sources of timing defects that may affect such interconnects such as those due to breaks or opens [12,3,34].…”

Section: Motivationmentioning

confidence: 99%

See 1 more Smart Citation

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Mele

Favalli

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The first one collects all the principal information divided in four classes: [16], whose blif representation is shown in figure 5. 3.…”

Section: Methodsmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Mele

Favalli

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Here a 1.5 M resistive defect produces a read disturb fault after the fifth consecutive read access performed at-speed (cycle time = 3 ns). The sensitization sequence for this fault is 1w0(r0) 5 , i.e. a w0 followed by five r0.…”

Section: • Incorrect Read Fault (Irf)mentioning

confidence: 99%

“…Many links have been established between delay faults and resistive-open defects [5,14]. Resistiveopens generally cause timing-dependent faults.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Borri¹,

Hage-Hassan²,

Dilillo

et al. 2005

J Electron Test

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Abstract. This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 µm embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.

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“…This poses reliability concerns and motivates the use of small delay testing for new technologies. R ESISTIVE opens are common manufacturing failures that induce delay faults of different degrees and cause potential reliability risks due to their partial break-like nature [1], [2], [3], [4]. Therefore screening for such faults is important to reduce test escapes, infant mortality failures and reject rates.…”

mentioning

confidence: 99%

Multivoltage Aware Resistive Open Fault Model

Mohammadat

Ali

Hussin

et al. 2014

IEEE Trans. VLSI Syst.

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Abstract-Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs and their behavior exhibits major dependencies on the supply voltage and test patterns. The widespread utilization of multiple supply voltages in contemporary VLSI designs poses a critical concern as to whether conventional models for resistive opens would still be effective. This is because conventional models do not explicitly model the VDD effect on fault behavior and detectability. Based on experimental analysis of ROFs in multi-VDD environment, we propose a voltage-aware model which divides the full range of open resistances (RO) into continuous behavioral intervals and three detectability ranges. The division of the behavior into intervals is based on monitoring the behavior change versus voltage across the resistance continuum, whereas the detectability ranges are based on finding minimum resistance for small and gross delay faults. It is highlighted that the detectable open resistance range is having a decreased trend with new technologies. Additionally it is shown that the observability of the unique increasing delay behavior with VDD for resistive open is reduced in new technologies. This poses reliability concerns and motivates the use of small delay testing for new technologies.

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Defect-based delay testing of resistive vias-contacts a critical evaluation

Cited by 112 publications

References 12 publications

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Multivoltage Aware Resistive Open Fault Model

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