Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can be utilized to guarantee security in electronic information. It remains to uphold to be resistive from most of the attacks. In this work, AES-128 encryption iterative architecture is designed to achieve minimum area and less hardware utilization. Reduced area is attained by introducing a renovated S-box structure into the AES algorithm. Furthermore, hardware utilization is minimized by incorporating the Vedic multiplier in the Mix column transformation of the AES Encryption process. The proposed encryption architecture is of 128-bit size and was executed on the Xilinx Spartan FPGA series, namely, Spartan 3, Virtex-4 and Virtex-5 devices. The optimization result exhibits that the proposed S-box technique has a smaller area than other existing conventional works.
Life of human being and animals depend on the environment which is surrounded by plants. Like human beings, plants also suffer from lot of diseases. Plant gets affected by completely including leaf, stem, root, fruit and flower; this affects the normal growth of the plant. Manual identification and diagnosis of plant diseases is very difficult. This method is costly as well as time-consuming so it is inefficient to be highly specific. Plant pathology deals with the progress in developing classification of plant diseases and their identification. This work clarifies the identification of plant diseases using leaf images caused by bacteria, viruses and fungus. By this method it can be identified and control the diseases. To identify the plant leaf disease Adaptive Neuro Fuzzy Inference System (ANFIS) was proposed. The proposed method shows more refined results than the existing works.
This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.
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