FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

Murugan, C. Arul; Karthigaikumar, P.; Priya, S. Sridevi Sathya

doi:10.1080/00051144.2020.1816388

Cited by 32 publications

(23 citation statements)

References 29 publications

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“…A combined-block strategy employing Key Expansion design for improving the throughput and for minimizing the power usage was introduced by Kalaiselvi [22]. In numerous additional scientific studies [23][24][25][26][27], various degrees of pipelined architectures were suggested. Granado et al [28] created a high-speed AES formula execution for Wi-FI Protected Access 2 (WPA2) systems.…”

Section: Literature Reviewmentioning

confidence: 99%

Advanced FPGA Implementation of AES Algorithm

2021

IJETER

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Along with the enhance in computation as well as information safe-keeping in cloud servers, the requirement for a devoted computer hardware accelerator with regard to encryption is arising to be able to decrease the processor work. Highly efficient Advanced Encryption Standard (AES) 128-bit implementation, that could be utilized as an accelerator. In this research paper resource optimization and higher throughput were obtained. Memory segmentation is actually carried out to be able to assign several ports for simultaneous information accessibility. When algorithm is in proceed and examined time delay and initiation time period of various procedures, with regard to every crucial route delay, a fresh multistage solitary initiation time period sub-pipelined structure is suggested for making the initiation time period to a single for smallest route latency. Consequently, almost all operations in AES could be started within a single clock cycle and also can easily accept input in each and every clock cycle. The suggested approach while examined on latest Field Programmable Gate Array (FPGA) XC7VX690T unit that offers a throughput of 104.06 Gbps at a highest frequency of 813MHz and also 1.23-ns route delay. The useful resource utilization is reduced whenever compared along with other alternatives. The suggested method offers 30.74Mbps efficiency on device, which usually was 27.13% much more compared to the best efficiency documented in an earlier research study

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Section: Literature Reviewmentioning

confidence: 99%

Advanced FPGA Implementation of AES Algorithm

2021

IJETER

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“…Arul et al [44] developed the Iterative Structure of the AES (ISAES) for lessening the hardware resources. The architecture of renovated S-box was used in the AES to minimize the area.…”

Section: Introductionmentioning

confidence: 99%

“…The hardware resources also increased because of AES design using non-pipelined stages [41]. Due to the high delay, the operating frequency is decreased in the AES architecture [44]. The area of the overall AES is increased because of the replication of linear function and independent operation [45].…”

Section: Introductionmentioning

confidence: 99%

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

Kumar

Balmuri²,

Marchewka

et al. 2021

Sensors

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Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

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“…On the other hand, symmetric cryptography is less complex and executes faster than asymmetric cryptography, and so it has been accepted as an industry-standard cryptographic algorithm and is being widely used to secure sensitive, secret, or classified information in government, healthcare, banking, and other industries. Previously researchers proposed plenty of symmetric cryptographic algorithms [ 7 – 11 ]. Advanced Encryption Standard (AES) is one of the most secured and chosen US NIST of USA Govt for its military among the multiple cryptographic algorithms.…”

Section: Introductionmentioning

confidence: 99%

Design of a BIST implemented AES crypto-processor ASIC

2021

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This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

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FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

Cited by 32 publications

References 29 publications

Advanced FPGA Implementation of AES Algorithm

Advanced FPGA Implementation of AES Algorithm

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

Design of a BIST implemented AES crypto-processor ASIC

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