Multilevel programing and charge transport characteristics of intrinsic SiOx-based resistive switching memory are investigated using TaN/SiOx/n++Si (MIS) and TiW/SiOx/TiW (MIM) device structures. Current transport characteristics of high- and low-resistance states (HRS and LRS) are studied in both device structures during multilevel operation. Analysis of device thermal response demonstrates that the effective electron energy barrier is strongly dependent on the resistance of the programed state, with estimates of 0.1 eV in the LRS and 0.6 eV in the HRS. Linear data fitting and conductance analyses indicate Poole-Frenkel emission or hopping conductance in the low-voltage region, whereas Fowler-Nordheim (F-N) or trap-assisted tunneling (TAT) is indicated at moderate voltage. Characterizations using hopping transport lead to hopping distance estimates of ∼1 nm in the LRS for both device structures. Relative permittivity values (εr) were extracted using the Poole-Frenkel formulism and estimates of local filament temperature, where εr values were ∼80 in the LRS and ∼4 in the HRS, suggesting a strongly polarized medium in the LRS. The onset of F-N tunneling or TAT corresponds to an observed “overshoot” in the I-V response with an estimated threshold of 1.6 ± 0.2 V, in good agreement with reported electro-luminescence results for LRS devices. Resistive switching is discussed in terms of electrochemical reactions between common SiO2 defects, and specific defect energy levels are assigned to the dominant transitions in the I-V response. The overshoot response in the LRS is consistent with TAT through either the Eγ' oxygen vacancy or the hydrogen bridge defect, both of which are reported to have an effective bandgap of 1.7 eV. The SET threshold at ∼2.5 V is modeled as hydrogen release from the (Si-H)2 defect to generate the hydrogen bridge, and the RESET transition is modeled as an electrochemical reaction that re-forms (SiH)2. The results provide further insights into charge transport and help identify potential switching mechanisms in SiOx-based unipolar resistive switching memory.

The physical mechanisms of unipolar resistive switching (RS) in SiOx-based resistive memory are investigated using TaN/SiOx/n++Si and TiW/SiOx/TiW device structures. RS is independent of SiOx thickness and device area, confirming that RS occurs in a localized region along a filamentary pathway. Results from experiments varying electrode type, series resistance, and the oxygen content of SiOxNy materials show the potential to optimize switching performance and control device programming window. Device materials with stoichiometry near that of SiO2 are found to have better operating stability as compared to extrinsic, N-doped SiOxNy materials. The results provide further insight into the physical mechanisms of unipolar operation and lead to a localized switching model based on electrochemical transitions involving common SiOx defects. High-temperature data retention measurements for over 104 s in high- and low-resistance states demonstrate the potential for use of intrinsic SiOx RS devices in future nonvolatile memory applications.

Articles you may be interested inIntrinsic SiOx-based unipolar resistive switching memory. II. Thermal effects on charge transport and characterization of multilevel programing Intrinsic SiOx-based unipolar resistive switching memory. I. Oxide stoichiometry effects on reversible switching and program window optimizationThe resistive switching characteristics and mechanism in active SiO x -based resistive switching memory have been investigated by using a simple TaN/SiO 2 /n þþ Si-substrate test structure. Controlling the oxygen content in SiO x layer not only improved device yield but also stabilized electrical switching characteristics. The current transport behavior in high-and low-resistance states, thickness effect in SiO x layer, device area effect, and multilevel effect by controlling compliance current limitation and stopped voltage values have been studied. The results indicate that resistive switching occurs in a localized region along a filament, rather than uniformly throughout the bulk. A general current flow model for nonpolar SiO x -based resistive switching memory has been proposed, which provides a simple physical concept to describe the resistive switching behavior and provides additional insights into optimization of resistive switching memory devices. V C 2012 American Institute of Physics. [http://dx.

We report on a highly compact, one diode-one resistor (1D-1R) nanopillar device architecture for SiOx-based ReRAM fabricated using nanosphere lithography (NSL). The intrinsic SiOx-based resistive switching element and Si diode are self-aligned on an epitaxial silicon wafer using NSL and a deep-Si-etch process without conventional photolithography. AC-pulse response in 50 ns regime, multibit operation, and good reliability are demonstrated. The NSL process provides a fast and economical approach to large-scale patterning of high-density 1D-1R ReRAM with good potential for use in future applications.

Electroforming and resistive switching data are presented and models are given addressing the unusual operating features of SiO2 resistive memory.

The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities of the brain, may provide such a shift. Many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop neuromorphic computing platforms. These platforms are being designed using various hardware technologies, including the well‐established complementary metal‐oxide semiconductor (CMOS), and emerging memristive technologies such as SiOx‐based memristors. Herein, recent progress in CMOS, SiOx‐based memristive, and mixed CMOS‐memristive hardware for neuromorphic systems is highlighted. New and published results from various devices are provided that are developed to replicate selected functions of neurons, synapses, and simple spiking networks. It is shown that the CMOS and memristive devices are assembled in different neuromorphic learning platforms to perform simple cognitive tasks such as classification of spike rate‐based patterns or handwritten digits. Herein, it is envisioned that what is demonstrated is useful to the unconventional computing research community by providing insights into advances in neuromorphic hardware technologies.

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