2013
DOI: 10.1021/nl404160u
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Integrated One Diode–One Resistor Architecture in Nanopillar SiOx Resistive Switching Memory by Nanosphere Lithography

Abstract: We report on a highly compact, one diode-one resistor (1D-1R) nanopillar device architecture for SiOx-based ReRAM fabricated using nanosphere lithography (NSL). The intrinsic SiOx-based resistive switching element and Si diode are self-aligned on an epitaxial silicon wafer using NSL and a deep-Si-etch process without conventional photolithography. AC-pulse response in 50 ns regime, multibit operation, and good reliability are demonstrated. The NSL process provides a fast and economical approach to large-scale … Show more

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Cited by 101 publications
(63 citation statements)
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References 40 publications
(58 reference statements)
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“…Compared with passive arrays that use highly nonlinear memristors 14,[37][38][39] or discrete selector devices [40][41][42][43] to mitigate the sneak path current problem, the 1T1R scheme has a lower packing density (2.5 times the cell area). However, it allows us to independently access memristors with a linear current-voltage (I-V) relation in an array with the transistor gate control, so each memristor's conductance can be precisely tuned.…”
Section: × 64 Memristor Crossbarsmentioning
confidence: 99%
“…Compared with passive arrays that use highly nonlinear memristors 14,[37][38][39] or discrete selector devices [40][41][42][43] to mitigate the sneak path current problem, the 1T1R scheme has a lower packing density (2.5 times the cell area). However, it allows us to independently access memristors with a linear current-voltage (I-V) relation in an array with the transistor gate control, so each memristor's conductance can be precisely tuned.…”
Section: × 64 Memristor Crossbarsmentioning
confidence: 99%
“…Several recent reports describe using SiO 2 as the active switching medium in resistive switching memory devices [46][47][48][49]. We have further demonstrated a Si diode (1D) with low reverse-bias current integrated with a SiO x -based memory element (1R) using nanosphere lithography and deep Si etching to pattern a P ++ /N + /N ++ epitaxial Si wafer [50].…”
Section: Introductionmentioning
confidence: 98%
“…[25][26][27][28] Thus, the unit memory cell with nonlinear current characteristics would be most desirable for processing and device simplicities. 14 In one of our previous reports, Si 3 N 4 -based RRAM device with embedded tunnel oxide was demonstrated, which exhibited a high nonlinearity (> 10 2 ) even without an additional access device. 14 We have focused on developing RRAM cells in the MIS structure which has a number of advantages over the conventional metal-insulator-metal (MIM) structure.…”
mentioning
confidence: 94%
“…14 In one of our previous reports, Si 3 N 4 -based RRAM device with embedded tunnel oxide was demonstrated, which exhibited a high nonlinearity (> 10 2 ) even without an additional access device. 14 We have focused on developing RRAM cells in the MIS structure which has a number of advantages over the conventional metal-insulator-metal (MIM) structure. [16][17][18][19] In the MIS structure, the Si bottom electrode (BE) can be easily integrated through CMOS technology without complicating the backend-of-the-line (BEOL) [29][30][31][32][33][34] and has higher flexibility in physical design of RRAM devices by using an anisotropic wet etching process.…”
mentioning
confidence: 94%
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