The thermal and spatial variation of Cu through silicon via (TSV)-induced stress in 300mm Si wafers has been investigated for both isolated TSVs and TSV arrays using topdown and cross-sectional spectral microRaman imaging. The TSV-induced stress in Si results from plastic yield of the Cu, is compressive in the immediate vicinity of the TSV, and transitions to a tensile state at larger separations -in quantitative agreement with finite element modeling (FEM). TSV arrays (linear and square) lead to substantial tensile stress enhancement within the array.Moreover, thermal annealing showed that the intraarray Si stress field became more compressive with increased post-CMP thermal annealing while the Si stress-field external to the arrays exhibited little change. This may open potential avenues for reduction of TSV-induced Si stress in 3DICs.
Polyurethane (PU) pad debris is identified as one of the major polish residue defects in Cu CMP processes when a barrier pad is conditioned. AES analysis of the debris confirms the organic nature of such defects while FT-IR analysis reveals the characteristic peaks of polyurethane from the pad debris. Hybrid cleans (i.e. acidic plus basic cleans) and basic cleans can both remove the pad debris effectively. The efficiency of basic-only cleans can be improved by increasing time and/or chemistry concentration in the brush modules. The PU pad can endure harsh chemical environments at both low and high pH without any detectable decomposition or morphological changes. The advantages and disadvantages of acidic vs. basic cleans are discussed and the cleaning mechanisms of pad debris PR are elucidated.
The thermal and spatial variation of Cu TSV-induced stress has been investigated for 1×4 arrays of 5 m diameter × 50 m TSVs using microRaman imaging. Following post-CMP annealing the measured Si Raman shift outside the TSV array is slightly modified. In strong contrast, the Si Raman shift midway between TSVs transitions from a tensile to compressive state as the annealing temperature increases. Topographic analysis implies this shift is associated with thermally-induced Cu extrusion.
INTRODUCTIONThe development of 3D interconnection methods for future generations of integrated circuits is important for meeting further scaling demands [1-2]. 3D die stacking can also improve the areal efficiency and functionality of future chips [3]. The use of copper through-silicon vias (Cu TSVs) is a highly promising avenue for 3D integration, but the differences in thermo-mechanical properties between copper and silicon can lead to substantial TSV-induced stress profiles in the surrounding Si. The coupling between these stress fields and the carrier mobility in Si have raised concerns about the impact of TSVs on the performance of nearby devices [4]. One important source of TSV-induced stress in Si is the plastic yield of Cu at elevated processing temperatures. The large difference between the coefficients of thermal expansion in Cu and Si can result in the generation of thermally-induced stress at high temperatures that exceeds the Cu yield stress. Upon cooling, the residual strain in Cu associated with high temperature plastic yield creates a residual stress profile in the nearby Si. This information should be incorporated into Si device simulations for modeling and design specifications.
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