Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits

Backes, Benjamin; McDonough, Colin; Smith, Larry; Wang, Wei; Geer, Robert

doi:10.1007/s10836-011-5242-7

Cited by 9 publications

(6 citation statements)

References 13 publications

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“…Inside the array, the minimum TSVinduced tensile stress in the Si (~ 20-22 MPa) occurs midway between the TSVs. The observed stress profile is consistent with previous measurements on similar arrays [6].…”

Section: Resultssupporting

confidence: 92%

“…The shift of this band is a function of the crystalline and experimental geometries for arbitrary strain, necessitating the full secular equation to be solved to extract the local stress sate [5]. For the Cu TSV geometry considered here, the stress state in the Si near the SiO 2 /Si interface is approximately biaxial [6]. This permits a straightforward analytical solution [5], with the Si stress,  [MPa]  -434* [cm-1 ], where  is the difference between the measured Raman peak position and the unstrained value.…”

Section: Methodsmentioning

confidence: 99%

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Thermal and spatial dependence of TSV-induced stress in Si

McDonough

Backes

Wang

et al. 2011

2011 IEEE International Interconnect Technology Conference

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The thermal and spatial variation of Cu TSV-induced stress has been investigated for 1×4 arrays of 5 m diameter × 50 m TSVs using microRaman imaging. Following post-CMP annealing the measured Si Raman shift outside the TSV array is slightly modified. In strong contrast, the Si Raman shift midway between TSVs transitions from a tensile to compressive state as the annealing temperature increases. Topographic analysis implies this shift is associated with thermally-induced Cu extrusion. INTRODUCTIONThe development of 3D interconnection methods for future generations of integrated circuits is important for meeting further scaling demands [1-2]. 3D die stacking can also improve the areal efficiency and functionality of future chips [3]. The use of copper through-silicon vias (Cu TSVs) is a highly promising avenue for 3D integration, but the differences in thermo-mechanical properties between copper and silicon can lead to substantial TSV-induced stress profiles in the surrounding Si. The coupling between these stress fields and the carrier mobility in Si have raised concerns about the impact of TSVs on the performance of nearby devices [4]. One important source of TSV-induced stress in Si is the plastic yield of Cu at elevated processing temperatures. The large difference between the coefficients of thermal expansion in Cu and Si can result in the generation of thermally-induced stress at high temperatures that exceeds the Cu yield stress. Upon cooling, the residual strain in Cu associated with high temperature plastic yield creates a residual stress profile in the nearby Si. This information should be incorporated into Si device simulations for modeling and design specifications.

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Section: Resultssupporting

confidence: 92%

Section: Methodsmentioning

confidence: 99%

Thermal and spatial dependence of TSV-induced stress in Si

McDonough

Backes

Wang

et al. 2011

2011 IEEE International Interconnect Technology Conference

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“…One potential disadvantage of 3D integration is the emergence of TSV-induced stress within the Si that can alter important transistor electrical properties such as mobility within the proximity of a TSV [7]. Transistor mobility has a direct correlation to the drain current produced by a metal-oxide-semiconductor (MOS) transistor.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the maximum number of functional transistors per die increases by reducing the transistor KOZ. Previously, authors have investigated transistor KOZ for shield‐less TSVs using both analytical and experimental methods including the microRaman spectroscopy technique [7, 8]. However, coaxial TSV transistor KOZs have only been investigated using analytical methods to predict behaviour [9].…”

Section: Introductionmentioning

confidence: 99%

Experimental characterisation of coaxial TSV transistor keep out zones

Adamshick

Northrup

Liehr

2018

Micro & Nano Letters

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Three-dimensional (3D) integration is an emerging technology that aims to achieve efficient packaging of the multifunctional silicon (Si) die within a single chip package. This system in package approach achieves connectivity between the individual Si die using through Si via (TSV) technology. Coaxial TSVs have emerged as the preferred 3D interconnect for high-frequency packaging applications due to their superior high-frequency electrical characteristics. The interconnect utilises a copper shield to prevent noise and unwanted signal coupling to occur within the Si substrate. However, a potential disadvantage of 3D integration is the large transistor keep-out-zones (KOZs) required to prevent transistor variability caused by thermally induced stress due to the copper-based TSVs in the Si substrate. Currently, only analytical models exist that predict KOZs for various coaxial TSV configurations and determining the precise KOZ is critical to minimise interconnect footprint that results in increased costs due to reductions in Si die area for integrated circuit designers. For the first time, the work has characterised the thermomechanical behaviour of fabricated coaxial TSVs utilising the microRaman spectroscopy technique to define transistor KOZ for both analogue and digital circuital applications.

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“…The CTE mismatch between copper and silicon causes inevitable stress on silicon and results in material failure. [10][11][12][13][14][15] It will also affect the performance of devices which are around the TSV and reduce the life of the electronic device. [16,17] Furthermore, the design parameters, such as the thickness and materials of Cu diffusion barrier and liner, have an impact on the mechanical reliability.…”

Section: Introductionmentioning

confidence: 99%

An analytical model of thermal mechanical stress induced by through silicon via

Dong¹,

Tao²,

Zhao³

et al. 2015

Chinese Phys. B

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We present an accurate through silicon via (TSV) thermal mechanical stress analytical model which is verified by using finite element method (FEM). The results show only a very small error. By using the proposed analytical model, we also study the impacts of the TSV radius size, the thickness, the material of Cu diffusion barrier, and liner on the stress. It is found that the liner can absorb the stress effectively induced by coefficient of thermal expansion mismatch. The stress decreases with the increase of liner thickness. Benzocyclobutene (BCB) as a liner material is better than SiO 2 . However, the Cu diffusion barrier has little effect on the stress. The stress with a smaller TSV has a smaller value. Based on the analytical model, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed FEM simulations. The analytic solutions of stress of two TSVs and three TSVs have high precision against the finite element result.

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Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits

Cited by 9 publications

References 13 publications

Thermal and spatial dependence of TSV-induced stress in Si

Thermal and spatial dependence of TSV-induced stress in Si

Experimental characterisation of coaxial TSV transistor keep out zones

An analytical model of thermal mechanical stress induced by through silicon via

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