Thermal and spatial profiling of TSV-induced stress in 3DICs

McDonough, Colin; Backes, Benjamin; Wang, Wei; Geer, Robert

doi:10.1109/irps.2011.5784530

Cited by 6 publications

(4 citation statements)

References 12 publications

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“…The key premise of this analysis is to perform simultaneous power and thermal analysis. To do so, temperature dependent resistivity is used and expressed as (7) where is the electrical resistivity at which is 27 C and is the temperature coefficient of electrical resistance [23]. As temperature increases, the electrical resistivity of the conductors goes up and eventually impacts power supply noise.…”

Section: Electrical Modelmentioning

confidence: 99%

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

Todri

Kundu

Girard

et al. 2013

IEEE Trans. VLSI Syst.

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International audience3-D integration presents a path to higher performance, greater density, increased functionality and heterogeneous technology implementation. However, 3-D integration introduces many challenges for power and thermal integrity due to large switching currents, longer power delivery paths, and increased parasitics compared to 2-D integration. In this work, we provide an in-depth study of power and thermal issues while incorporating the physical design characteristics unique to 3-D integration. We provide a qualitative perspective of the power and thermal dissipation issues in 3-D and study the impact of Through Silicon Vias (TSVs) size for their mitigation. We investigate and discuss the design implications of power and thermal issues in the presence of decoupling capacitors, TSV/on-die/package parasitics, various resonance effects and power gating. Our study is based on a ten-tier system utilizing existing 3-D technology specifications. Based on detailed power distribution and heat dissipation models, we present a comprehensive analysis of TSV tapering for alleviating power and thermal integrity issues in 3-D ICs

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Section: Electrical Modelmentioning

confidence: 99%

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

Todri

Kundu

Girard

et al. 2013

IEEE Trans. VLSI Syst.

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“…[8]. A semi-analytical stress model of TSV is proposed and applied in the calculation of multi-TSVs thermal-stress at a given point on the substrate [9] . The above works make a great contribution on exploring TSV thermal-stress modeling, but their models are all established under the isotropic assumption, which has the computation error in the stress distribution of silicon substrate.…”

Section: Introductionmentioning

confidence: 99%

An anisotropic thermal-stress model for through-silicon via

Liu

Shan

2018

J. Semicond.

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A two-dimensional thermal-stress model of through-silicon via (TSV) is proposed considering the anisotropic elastic property of the silicon substrate. By using the complex variable approach, the distribution of thermal-stress in the substrate can be characterized more accurately. TCAD 3-D simulations are used to verify the model accuracy and well agree with analytical results (< ±5%). The proposed thermal-stress model can be integrated into stress-driven design flow for 3-D IC , leading to the more accurate timing analysis considering the thermal-stress effect.

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“…[25][26][27][28][29][30][31][32] Micro-Raman spectroscopy is more suitable from a practical point of view. Since the probing depth of Raman spectroscopy is dependent on the excitation wavelength, choice of proper excitation wavelength is very important.…”

Section: Introductionmentioning

confidence: 99%

Multiwavelength Raman characterization of silicon stress near through-silicon vias and its inline monitoring applications

Yoo¹,

Kim

Han

2014

J. Micro/Nanolith. MEMS MOEMS

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Abstract. Characterization of silicon stress near copper (Cu)-filled through-silicon via(s) (TSVs) was demonstrated using high-resolution micro-Raman spectroscopy. For depth profiling of Si stress distribution near TSVs, a polychromator-based, multiwavelength excitation Raman measurement with different probing depths was used. The design concept of the polychromator-based, multiwavelength micro-Raman spectroscopy system, including the importance of the high-spectral resolution and multiwavelength excitation capability in three-dimensional (3-D) Si stress characterization, was described. Silicon stress near Cu-filled TSVs, with various sizes and layouts, was measured and analyzed before and after Cu annealing steps. Main factors impacting Si stress near Cu-filled TSVs are analyzed based on Raman characterization results on various types of TSV structures, layouts, and Cu annealing conditions. Large variations in Si stress in TSV arrays were measured in wafers with poor Cu fill characteristics and in wafers annealed in nonoptimized conditions. The Cu annealing sequence and annealing conditions are found to be significantly important for managing Si stress and the reliability of Cu-filled TSVs. Substantially lower Si stress was measured near Cu-filled TSVs with voids. Multiwavelength microRaman spectroscopy can be used as a very effective noncontact, nondestructive, inline TSV process and Si stress monitoring technique.

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Thermal and spatial profiling of TSV-induced stress in 3DICs

Cited by 6 publications

References 12 publications

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

An anisotropic thermal-stress model for through-silicon via

Multiwavelength Raman characterization of silicon stress near through-silicon vias and its inline monitoring applications

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