Multiwavelength Raman characterization of silicon stress near through-silicon vias and its inline monitoring applications

Abstract

Abstract. Characterization of silicon stress near copper (Cu)-filled through-silicon via(s) (TSVs) was demonstrated using high-resolution micro-Raman spectroscopy. For depth profiling of Si stress distribution near TSVs, a polychromator-based, multiwavelength excitation Raman measurement with different probing depths was used. The design concept of the polychromator-based, multiwavelength micro-Raman spectroscopy system, including the importance of the high-spectral resolution and multiwavelength excitation capability in three-dimensional (3-D) Si stress characterization, was described. Silicon stress near Cu-filled TSVs, with various sizes and layouts, was measured and analyzed before and after Cu annealing steps. Main factors impacting Si stress near Cu-filled TSVs are analyzed based on Raman characterization results on various types of TSV structures, layouts, and Cu annealing conditions. Large variations in Si stress in TSV arrays were measured in wafers with poor Cu fill characteristics and in wafers annealed in nonoptimized conditions. The Cu annealing sequence and annealing conditions are found to be significantly important for managing Si stress and the reliability of Cu-filled TSVs. Substantially lower Si stress was measured near Cu-filled TSVs with voids. Multiwavelength microRaman spectroscopy can be used as a very effective noncontact, nondestructive, inline TSV process and Si stress monitoring technique.

Investigation of Plasma Enhanced Chemical Vapor Deposition Chamber Mismatching by Photoluminescence and Raman Spectroscopy

“…The Raman probing depths in Si for 457.9, 488.0 and 514.5 nm laser beam are ∼290 nm, ∼490 nm and ∼645 nm, respectively. [23][24][25] Weighted average stress of Si from the SiO 2 /Si interface, over the Raman probing depths, can be measured at a given excitation wavelength. [23][24][25] By measuring the Raman signal from Si under different excitation wavelengths, Si lattice stress under the SiO 2 and its distribution into bulk Si can be evaluated.…”

“…[23][24][25] Weighted average stress of Si from the SiO 2 /Si interface, over the Raman probing depths, can be measured at a given excitation wavelength. [23][24][25] By measuring the Raman signal from Si under different excitation wavelengths, Si lattice stress under the SiO 2 and its distribution into bulk Si can be evaluated. Figure 2 summarizes the SiO 2 film thickness, calculated from ellipsometry measurements, using an He-Ne laser (633 nm), RTPL wafer maps and RTPL line scan results, under 650 and 827 nm excitation, in the Y-direction from the wafer notch.…”

“…Multiwavelength microRaman system (MRS-300) is described elsewhere. [16][17][18]21,[23][24][25] The focused laser beam diameter at the wafer surface was in the range of ∼1 μm. The Raman probing depths in Si for 457.9, 488.0 and 514.5 nm laser beam are ∼290 nm, ∼490 nm and ∼645 nm, respectively.…”

Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects

“…A nondestructive technique that characterizes the stresses without affecting the material under investigation is particularly desirable. 22,23 Various theoretical models and semianalytical approaches combined with micro-Raman spectroscopy have been used for analyzing near surface stresses in ETWI structures and suggest that interfacial delamination is a potential failure mechanism for ETWI structures. 15 Nondestructive inspection techniques such as scanning GHz acoustic microscopy, optical diffraction, spectral reflectometry, and x-ray tomography are being increasingly used to study voids in TSVs, measure via dimensions (both lateral and depth) and examine local changes in morphology at the edge or bottom of the via.…”

Effects of Stress and Electromigration on Microstructural Evolution in Microbumps of Three-Dimensional Integrated Circuits

“…The management of stresses occurring at multiple scales is a key issue that must be addressed to ensure the high performance and reliability of 3D integrated circuits (ICs) [1]- [5]. At the package level, stresses can cause failures within bumps, cracks within dies, delaminations from dielectric layers, etc.…”