Nanoimprint lithography was combined with glancing angle deposition (GLAD) of titanium dioxide to fabricate a square spiral columnar film with a bandgap in the visible spectral range. Nanoimprint stamps were fabricated with seed spacing ranging from 80 to 400 nm, and four periods of square spiral film were deposited on top of the 320 nm array of seeds. The ratio of lattice spacing, vertical pitch and spiral arm swing was chosen as a : P : A = 1 : 1.35 : 0.7 and the deposition angle was fixed at 86° to maximize the square spiral film’s bandgap. Reflectivity measurements show that the fabricated structure exhibit a pseudo-gap centered at around 600 nm wavelength, in good agreement with finite difference electromagnetic simulations. The absence of a full 3D bandgap is due the deviation of GLAD columns’ cross-section from the optimal one, which has to be highly elongated in the deposition plane. However, simulations show that a geometry close to the fabricated one will produce a full 3D bandgap, if the structure is inverted. The material refractive index in such an inverted photonic crystal can be as low as n = 2.15.
Reflectivity of a photonic crystal device fabricated by glancing angle deposition may be reversibly altered by infiltration with an absorbing dye solution. An electric field controls the dye ion motion through the photonic crystal. Rapid reflectance changes up to 0.4 in the crystal’s optical band gap are demonstrated. The time evolution of the dye movement process is examined and its operation described. This work may have applications for a passive optical display.
Electrical through-wafer interconnect technologies such as vertical through-silicon vias (TSVs) are essential in order to maximize performance, optimize usage of wafer real estate, and enable three-dimensional packaging in leading edge electronic and microelectromechanical systems (MEMS) products. Although copper TSVs have the advantage of low resistance, highly doped polysilicon TSVs offer designers a much larger range of processing options due to the compatibility of polysilicon with high temperatures and also with the full range of traditional CMOS processes. Large stresses are associated with both Cu and polysilicon TSVs, and their accurate measurement is critical for determining the keep-out zone (KOZ) of transistors and for optimizing downstream processes to maintain high yield. This report presents the fabrication and stress characterization of 400-μm deep, 20-Ω resistance, high aspect ratio (25:1) polysilicon TSVs fabricated by deep reactive ion etching (DRIE) followed by low-pressure chemical vapor deposition (LPCVD) of polysilicon with in-situ boron doping. Micro-Raman imaging of the wafer surface showed a maximum stress of 1.2 GPa occurring at the TSV edge and a KOZ of ∼9 to 11 μm. For polysilicon TSVs, the stress distribution in the TSVs far from the wafer surface(s) was not previously well-understood due to measurement limitations. Raman spectroscopy was able to overcome this limitation; a TSV cross section was examined and stresses as a function of both depth and width of the TSVs were collected and are analyzed herein. An 1100°C postanneal was found to reduce average stresses by 40%.
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