Beak-Hyung Cho scite author profile

In mobile systems, the demand for the energy saving continues to require a low power memory sub-system. During the last decade, the floating-gate flash memory has been an indispensable low power memory solution. However, NOR flash memory has begun to show difficulties in scaling due to the device's reliability and yield issues. Over the past few years, phase-change random access memory (PRAM) has emerged as an alternative non-volatile memory (NVM) owing to its promising scalability and low cost process [1,2]. In this paper, a PRAM, implemented in a 58nm PRAM process with a low power double-data-rate nonvolatile memory (LPDDR2-N) interface, is presented [3].

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A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

Lee

Cho

et al. 2007

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Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory

Cho

et al. 2006

IEEE J. Solid-State Circuits

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Enhanced write performance of a 64Mb phase-change random access memory

Oh¹,

Cho²,

Cho³

et al.

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A 0.18 μm 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

Cho

Choi

et al.

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Beak-Hyung Cho

A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput

A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory

Enhanced write performance of a 64Mb phase-change random access memory

A 0.18 μm 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

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