A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

W-2W Current Steering DAC for Programming Phase Change Memory

“…A long set sweep current [1], SCD (stair case down) SET pulse programming [4], ASQ (arbitrary slow quench) [3] and/or MSPG (multiple step down pulse generation) [2] are different techniques for SET operation. These algorithms provide similar wave-shaping to SET current pulse and can be implemented through W-2W DAC.…”

“…It can also be used to generate the fast quench RESET current pulses. The complete programming sequence, for example the SCU (stair case up) algorithm with preparatory sequence [1], or write-verify scheme mentioned in [3], can be easily generated using the W-2W DAC. A simplified block diagram of PCM array programming, adapted from [2] is shown in Fig.…”

Understanding the influence of RESET current due to the active region of phase change memory

“…While phase transition processes are well understood and some PCM chips have been manufactured successfully [5,6], there are still some issues need to be solved. And power consumption is one of the most serious in all the issues.…”

A smart method of optimizing the read/write current on PCM array

“…Specifically, when a phase change material is heated to a high temperature with a long-pulse current, it crystallizes and reduces its resistance as SET operation. And a ramp down current is proved to be more effective [5]. To RESET a cell into a high resistance state, a current large enough to melt it is applied for a short period, and then abruptly cut off to quench the material into amorphous phase.…”