W-2W Current Steering DAC for Programming Phase Change Memory

Gupta, Shantanu; Saxena, Vishal; Campbell, Kristy A.; Baker, R. Jacob

doi:10.1109/wmed.2009.4816148

Cited by 17 publications

(5 citation statements)

References 10 publications

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“…(2) A/D Converters: Since the preferred velocity vectors are not to be changed after configuration, capacitance DACs that require refreshment are not preferred here. We adopted a W-2W transistor ladder [24] with a long transistor length to minimize current consumption. Two such DACs are implemented for each theta unit, connecting to the preferred velocity SRAMs.…”

Section: Design Of the Theta Chipmentioning

confidence: 99%

Neuromorphic place cells

Chen,

Nasrallah,

Etienne-Cummings

2024

Neuromorph. Comput. Eng.

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A neuromorphic SLAM system shows potential for more efficient implementation than its traditional counterpart. At the mean time a neuromorphic model of spatial encoding neurons in silicon could provide insights on the functionality and dynamic between each group of cells. Especially when realistic factors including variations and imperfections on the neural movement encoding are presented to challenge the existing hypothetical models for localization. We demonstrate a mixed-mode implementation for spatial encoding neurons including theta cells, egocentric place cells, and the typical allocentric place cells. Together, they form a biologically plausible network that could reproduce the localization functionality of place cells observed in rodents. The system consists of a theta chip with 128 theta cell units and an FPGA implementing 4 networks for egocentric place cells formation that provides the capability for tracking on a 11 by 11 place cell grid. Experimental results validate the robustness of our model when suffering from as much as 18% deviation, induced by parameter variations in analog circuits, from the mathematical model of theta cells. We provide a model for implementing dynamic neuromorphic SLAM systems for dynamic-scale mapping of cluttered environments, even when subject to significant errors in sensory measurements and real-time analog computation. We also suggest a robust approach for the network topology of spatial cells that can mitigate neural non-uniformity and provides a hypothesis for the function of grid cells and the existence of egocentric place cells.

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Section: Design Of the Theta Chipmentioning

confidence: 99%

Neuromorphic place cells

Chen,

Nasrallah,

Etienne-Cummings

2024

Neuromorph. Comput. Eng.

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“…Since the input of the neural amplifier is biased at ground, two NMOS transistors are used as tunable pseudo-resistors. The gate voltage of these NMOS transistors is globally generated from a W-2W voltage digital-to-analog converter (DAC) ( 98 ). These pseudo-resistors in conjunction with the electrode capacitance allow the neural amplifier to reject up-to 25 mV DC-offsets in the electrodes and provide a tunable high-pass corner.…”

Section: Section S1 Bisc Implant Designmentioning

confidence: 99%

Stable, chronic in-vivo recordings from a fully wireless subdural-contained 65,536-electrode brain-computer interface device

Jung,

Zeng,

Fabbri

et al. 2024

Preprint

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Minimally invasive, high-bandwidth brain-computer-interface (BCI) devices can revolutionize human applications. With orders-of-magnitude improvements in volumetric efficiency over other BCI technologies, we developed a 50-μm-thick, mechanically flexible micro-electrocorticography (μECoG) BCI, integrating 256×256 electrodes, signal processing, data telemetry, and wireless powering on a single complementary metal-oxide-semiconductor (CMOS) substrate containing 65,536 recording and 16,384 stimulation channels, from which we can simultaneously record up to 1024 channels at a given time. Fully implanted below the dura, our chip is wirelessly powered, communicating bi-directionally with an external relay station outside the body. We demonstrated chronic, reliable recordings for up to two weeks in pigs and up to two months in behaving non-human primates from somatosensory, motor, and visual cortices, decoding brain signals at high spatiotemporal resolution.

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“…The W-2W DACs linearity equations are discussed in equation 3and (4) [5]. In order to sum the errors as zero, the maximum positive and negative mismatch error is assumed at the current source corresponding to MSB (BN-1) and the bits from B0 through BN-2 respectively.…”

Section: B Inl and Dnlmentioning

confidence: 99%

Binary-Weighted DAC using W-2W Current Mirror Topology

Yogesha¹,

Bhandarkar²

2016

IJERT

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The paper presents an analysis and design of 3bit, 4-bit and 6-bit Binary-Weighted CMOS Digital to Analog Converters (DACs). All the DACs are implemented using various CMOS technologies such as 180 nm, 90 nm and 45 nm with the supply of 1.8 V. The INLs, DNLs and Power dissipation of each DAC is compared and analyzed. As the transistor sizing is scaled down, the area occupied by DACs decreases; resulting in lower power dissipation. Even INLs and DNLs are decreased with transistor scaling. Thus, as the technology is scaled down, the design archives a good trade-off between low INL, DNL and Power dissipation.

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W-2W Current Steering DAC for Programming Phase Change Memory

Cited by 17 publications

References 10 publications

Neuromorphic place cells

Neuromorphic place cells

Stable, chronic in-vivo recordings from a fully wireless subdural-contained 65,536-electrode brain-computer interface device

Binary-Weighted DAC using W-2W Current Mirror Topology

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