Enhanced write performance of a 64Mb phase-change random access memory

Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations

“…1(a). Some quenching technologies with different pulse shapes have been recently demonstrated [11,12,13], as shown in Fig. 2(a).…”

“…In this paper, we propose a new shape of set pulse developed from these previous work and the set-pulse shape is designed more properly than previous quenching technologies. The new set pulse is characterized by a continues step-down pulse for more efficient heating compared to the digital control quenching (Shape B) which sacrifices write time for pauses [11]. In addition, compared to the slope quenching technique (Shape C) [12,13], the new pulse features two parts where the first part is characterized by high current with short width and the second part is characterized by long width with falling steps.…”

Design challenges for prototypical and emerging memory concepts relying on resistance switching

“…Considering the high reset current required to switch chalcogenide material from crystalline to amorphous phase, access device must be able to drive high current during this operation. Access may be controlled by a bipolar junction transistor (BJT) [21], a diode [22] or a MOS transistor [23].…”

W-2W Current Steering DAC for Programming Phase Change Memory

“…Thus the ratio of conventional vs W-2W, N-bit binary weighted current steering DAC will be given by (2), where 2N/α account for switch size, where α is always > 1. The unit size, W/L, device employed in the circuit helps in achieving a symmetrical layout which reduces the mismatch in the circuit due to process variations.…”

“…A long set sweep current [1], SCD (stair case down) SET pulse programming [4], ASQ (arbitrary slow quench) [3] and/or MSPG (multiple step down pulse generation) [2] are different techniques for SET operation. These algorithms provide similar wave-shaping to SET current pulse and can be implemented through W-2W DAC.…”