A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput

Lee, Kwang-Jin; Cho, Beak-Hyung; Cho, Woo-Yeong; Kang, Seong-Hoon; Choi, Byoungdeog; Oh, Hansu; Lee, Chang‐Soo; Kim, Hye-Jin; Park, Joon-Min; Wang, Qi; Park, Mu-Hui; Ro, Yuhwan; Choi, Joon-Yong; Kim, Ki-Sung; Kim, Youngran; Shin, Ilgyou; Lim, Kiwon; Cho, Ho-Keun; Choi, Chang‐Hwan; Chung, Won-Ryul; Kim, Du-Eung; Yoon, Yong‐Jin; Yu, Kwang-Suk; Jeong, Gitae; Jeong, Hae-Yong; Kwak, Choong-Keun; Kim, Chang‐Hyun; Kim, Kinam

doi:10.1109/jssc.2007.908001

Cited by 162 publications

(83 citation statements)

References 7 publications

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“…Even though its cell size of the diode-switch is smaller, it needs higher operating voltage that compensates a voltage drop in the diode thus consuming more power than the MOS-switch PRAM. Figure 1 (a) shows both MOS-switch and diode-switch PRAM cells and Figure 1 (b) compares their current-voltage curves [2]. As you can see in this Figure 1 (b), the diode-switch PRAM has higher SET voltage by as much as the diode turning-on voltage than the MOS-switch thus its threshold voltage being increased higher than the MOS-switch.…”

Section: Introductionmentioning

confidence: 98%

“…Resistive memories such as PRAMs has been studied for many years because it has faster read and write access times and better scalability than FLASH memories [1,2,3,4,5]. Among various resistive memories, the diode-switch PRAM is currently replacing the MOS-switch one due to its small cell size without suffering loss of current driving capability [2].…”

Section: Introductionmentioning

confidence: 99%

“…Among various resistive memories, the diode-switch PRAM is currently replacing the MOS-switch one due to its small cell size without suffering loss of current driving capability [2]. Even though its cell size of the diode-switch is smaller, it needs higher operating voltage that compensates a voltage drop in the diode thus consuming more power than the MOS-switch PRAM.…”

Section: Introductionmentioning

confidence: 99%

“…Once the MOS-switch PRAM cell is read, a fixed amount of read current flows through the cell resistance and this current is converted to a voltage according to the stored cell resistance. The diode-switch PRAM, however, needs to precharge its sens- ing node in the beginning of read operation, because the diode is able to be turned on only when it is biased larger than its turning-on voltage [2]. After being precharged, the sensing node preserves its voltage when the cell resistance is the RESET state (∼100 kOhm) or the sensing node loses its voltage if the cell resistance is the SET state (∼1 kOhm).…”

Section: Introductionmentioning

confidence: 99%

“…This large power consumption during the read of the diode-switch PRAM is more magnified by variations in the cell resistance. The variations in the cell resistance that caused from various electrical and material reasons seem even larger than two orders of magnitude [2]. Let's look at Figure 1 (c) to see how the variations affect the power consumption in the read operation.…”

Section: Introductionmentioning

confidence: 99%

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Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs

Bong

Min

2009

IEICE Electron. Express

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Abstract:In this letter, a new read circuit with self-adjusted column pulse width is proposed for low-power applications of resistive memories. In the conventional read circuit, its column pulse width is determined by the worst-case value of the cell resistance variations thereby the pulse width being longer than required when the resistance variations are not in the worst case. In this paper, to alleviate power loss due to this long column pulse width, the column pulse width is selfadjusted according to the resistance variations thus unnecessary power loss being able to be reduced significantly. The power consumption during the read is expected to be less by 28.6% than the conventional circuit when the SET resistance is its mean value as large as 2 kΩ. The Monte Carlo simulation also shows that the power consumption of the proposed circuit is reduced by 25% in average than the conventional.

show abstract

Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs

Bong

Min

2009

IEICE Electron. Express

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Emerging Memory Structures for VLSI Circuits

Garzón¹,

Yavits²,

Lanuzza³

et al. 2022

Wiley Encyclopedia of Electrical and Electronics Engineering

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Ever since the emergence of the electrical computer and the Von Neumann model, computer architects have adhered to a well‐structured hierarchy of memory solutions, clearly trading off performance and capacity with cost. The ubiquitous memory technologies, dominated by SRAM, DRAM, Flash, and magnetic hard disks, are each situated in a well‐defined location within this hierarchy. However, as processes have scaled into deep nanometer feature sizes and the demand for larger capacities and bandwidths increases, these traditional options face tough challenges and may be limited in their ability to continue to provide the new requirements. New technologies, such as phase change memory (PCM), magnetic RAM (MRAM), and resistive RAM (RRAM), have been researched and developed over the recent past in an attempt to meet these demands and replace some or all of the traditional technologies. In this article, the primary technologies are overviewed, including those that currently fill the memory hierarchy pyramid, the primary candidates to join or replace them in the near‐term, and a number of newer candidates that may arise as legitimate solutions in the farther term. In addition, an overview of the current state of processing within the emerging memory technologies is provided, as an attempt to break free of the traditional Von Neumann paradigm to overcome the energy and performance bottlenecks in modern systems.

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Memory Select Devices

Chen

2014

Emerging Nanoelectronic Devices

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A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput

Cited by 162 publications

References 7 publications

Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs

Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs

Emerging Memory Structures for VLSI Circuits

Memory Select Devices

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