Memory Select Devices

Chen, An

doi:10.1002/9781118958254.ch12

Cited by 6 publications

(5 citation statements)

References 82 publications

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“…The sneak path problem is one of the main concerns in the construction of three-dimensional (3D) crossbar memory using BRS. , Here, the cross-talk interference between adjacent cells caused by sneak path current may result in misleading information . Several solutions have been suggested to overcome the sneak path problem, such as volatile switch, threshold switch, nonlinear device, diode-based solutions, etc. , Linn et al suggested the most effective way to resolve the sneak path problem, where two RS devices are connected antiserially so that if one device possesses LRS, then the other device is in HRS . Such a system is known as complementary resistive switching (CRS) .…”

Section: Introductionmentioning

confidence: 99%

“…28 Several solutions have been suggested to overcome the sneak path problem, such as volatile switch, threshold switch, nonlinear device, diode-based solutions, etc. 29,30 Linn et al suggested the most effective way to resolve the sneak path problem, where two RS devices are connected antiserially so that if one device possesses LRS, then the other device is in HRS. 31 Such a system is known as complementary resistive switching (CRS).…”

Section: ■ Introductionmentioning

confidence: 99%

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Complementary Resistive Switching Behavior in Tetraindolyl Derivative-Based Memory Devices

Sarkar¹,

Rahman²,

Banik³

et al. 2022

Langmuir

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Complementary resistive switching (CRS) devices are more advantageous compared to bipolar resistive switching (BRS) devices for memory applications as they can minimize the sneak path problem observed in the case of BRS having a crossbar array structure. Here, we report the CRS behavior of 1,4bis(di(1H-indol-3-yl)methyl)benzene (Indole1) molecules. Our earlier study revealed that Au/Indole1/Indium tin oxide (ITO) devices showed BRS under ambient conditions. However, the present investigations revealed that when the device is exposed to 353 K or higher temperatures, dynamic evolution of the Au/ Indole1/ITO device from BRS to CRS occurred with a very good memory window (∼10 3 ), data retention (5.1 × 10 3 s), stability (50 days), and device yield (∼ 60%). This work explores the application possibility of indole derivatives toward future ultradense resistive random access memory.

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Section: Introductionmentioning

confidence: 99%

Section: ■ Introductionmentioning

confidence: 99%

Complementary Resistive Switching Behavior in Tetraindolyl Derivative-Based Memory Devices

Sarkar¹,

Rahman²,

Banik³

et al. 2022

Langmuir

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“…The change of the memristor resistance is represented by the x(t) variable in Eq. (2). The speed of change of the boundary between the un-doped and doped layers is stated by dx / dt in Eq.…”

Section: Linear Drift Model and Window Functions Of The Memristormentioning

confidence: 99%

“…RESENT MEMORY Technologies such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), NAND flash and NOR flash will soon encounter challenges due to the continued scaling down of their designs [1]. Several types of memory technologies have been suggested for next generation memory devices including Spin-Transfer Torque RAM (STT-RAM), Phase Change Memory (PCM) and Resistive RAM (ReRAM) [2]. Researchers have focused on the Resistive Random Access Memory (RRAM) because of its ultra-high density production potential, faster switching speed and lower energy consumption for non-volatile memory applications.…”

Section: Introductionmentioning

confidence: 99%

A Generic Circuit Model for Memristor Based One Diode-One Resistor Devices

Gül

2019

Balkan Journal of Electrical and Computer Engineering

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Memristor-based resistive random access memory (RRAM) devices are very good competitors for next generation non-volatile crossbar memory applications. The sneak paths problem is one of the main constraints in fabricating crossbar memory devices. The one diode-one resistor (1D1R) structure design is effective for suppressing the sneak paths problem. Suitable circuit models are needed to simulate semiconductor structures. A general circuit model for memristor-based one diode-one resistor structures is proposed in this work. The Simulation Program with Integrated Circuit Emphasis (SPICE) environment was used to simulate the designed circuit. Well-known mathematical models such as those of Strukov, Biolek, Joglekar, Prodromakis and Zha were used to simulate the memristor component of the circuit. The current-voltage characteristics were obtained for different mathematical models. All results were compatible with the expected characteristics. The best fit characteristics were acquired using the Zha and Strukov models.

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“…The high processing temperature of the transistors makes it almost impossible to be used in 3D stacked memories. So the best approach to solve the sneak path problem is to use two-terminal thin-film-based selector devices that can be scaled laterally and stacked vertically together with a memristor (Chen, 2015;Burr et al, 2016).…”

Section: Introductionmentioning

confidence: 99%

Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration

Upadhyay

Blum

Maksymovych

et al. 2021

Front. Nanotechnol.

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Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN1+x/Ta2O5/TaN1+x/Pd layers that could achieve a NL of 3 × 105, which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta2O5/Ru based memristor on top of the proposed selector.

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Memory Select Devices

Cited by 6 publications

References 82 publications

Complementary Resistive Switching Behavior in Tetraindolyl Derivative-Based Memory Devices

Complementary Resistive Switching Behavior in Tetraindolyl Derivative-Based Memory Devices

A Generic Circuit Model for Memristor Based One Diode-One Resistor Devices

Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration

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