Human powered gyms are ones in which equipment can be used to generate electricity. Since the concept of a green or sustainable gym is recent, the potential of cardio equipment like treadmills, stationary bikes and rowing machines in generating energy are discussed in this paper. The power generated in a typical human powered gym, based on the equipment already existing in the market is analyzed. The amount of carbon dioxide emissions saved and the payback period for implementing this gym are also estimated. A survey was carried out to better understand how people would react to the presence of such gym. It was found that the energy-producing equipment in the gym not only benefit environmentally but also economically in the long run.
This brief describes a high-speed optoelectronic receiver implemented in 65 nm CMOS technology. The receiver utilizes only two clock phases instead of the four conventionally used in a quarter-rate clocking system. This two-clock phase system is enabled by a passive silicon photonic split and delay structure that eliminates the need for a quadrature clock phase generator and all the associated buffers. Moreover, the outputs of the receiver are demultiplexed which further helps reducing power consumption in the digital part of the system. The receiver also employs inter-stage AC coupling and is mounted on a high-speed printed circuit board (PCB). The impact of AC coupling and PCB parasitics is investigated. The functionality of the receiver is validated by high-speed optical measurements. The receiver achieves an error-free transmission (BER < 10 −12) up to a data rate of 12.5 Gb/s with an energy efficiency of 1.93 pJ/bit and sensitivity of −4 dBm from a 1 V supply.
This article presents the implementation of a novel 22-Gb/s energy-efficient optoelectronic receiver architecture in 65-nm CMOS for short-reach optical communication. The receiver incorporates four sub receivers with a two-bit integrating resettable front-end in each sub receiver. The inputs to two of the four sub receivers are optically delayed by one bit and two complementary quarter-rate clock phases are used to completely recover the data. The two-bit integrating low-bandwidth front end replaces the full-bandwidth transimpedance amplifier used in conventional optoelectronic receivers, resulting in improved energy efficiency. The low-bandwidth operation is enabled by using a capacitor at the input and by amplifying the two-bit integrated voltage with low-bandwidth voltage gain stages that require a bandwidth of only 35% of the operating data rate. The receiver performs a 1:4 demultiplexing operation by only using two quarter-rate clock phases instead of the four phases that are conventionally used in a quarter-rate clocking system. This clocking scheme reduces complexity while maintaining the same timing margin of the quarter-rate systems. This two-clock phase system is enabled by optical delay lines and splitters. The receiver is experimentally validated with a 1550-nm photodetector array wire bonded to the four inputs. The electronic part of the receiver achieves error-free transmission (BER < 10 −12) at 22 Gb/s with an energy efficiency of 1.43 pJ/bit and an average sensitivity of −7.8 dBm (or −6.2 dBm optically modulated amplitude) with a 1.09-V supply.
This letter describes the design and the measurements of a 15 GHz monopole antenna implemented in silicon photonics for inter-chip communication. The antenna is designed in HFSS with its radiation pattern simulated. To confirm its operation and experimentally demonstrate inter-chip communication, the antenna is fabricated in a commercial Silicon Photonics fabrication process. Measurements include s-parameter using a vector network analyzer, and inter-chip data transmission between two on-chip antennas. The inter-chip data transmission is demonstrated using an off-chip photodetector directly as a transmitter as a proof-of-concept. Results indicate the feasibility of a monolithically integrated photodiode-antenna system as a transmitter.
We investigate the monolithic integration of RF antennas onto a silicon-based integrated microwave photonics (IMWP) chip for short-range millimeter-wave (mmW) communication. The unification of antenna with photonic integrated circuits (PICs) reduces system loss for high data rate communication by eliminating parasitic interconnects. This integration of electronics (antenna) with photonics will be a key milestone leading to increased bandwidth capability and ubiquitous wireless links for emerging applications such as 5G, Internet of Things (IoT), autonomous vehicles, high data rate point-to-point communication, and wireless sensors. Through simulation above 20 GHz, we compare the transmission of three on-chip antenna structures designed in a commercial silicon photonics (SiPh) process and consider them for both inter and intra-chip communication. Results provide insight on the transmission gain variations relative to the antenna orientation from their distinct radiation pattern. The folded monopole structure provides superior gain, smaller footprint with layout flexibility, and good transmission spectra. The analysis supports the idea of a monolithic mmW transmitter integrated with on-chip antennas on IMWP chip.
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