A 12.5 Gb/s 1.93 pJ/Bit Optical Receiver Exploiting Silicon Photonic Delay Lines for Clock Phases Generation Replacement

Abstract

This brief describes a high-speed optoelectronic receiver implemented in 65 nm CMOS technology. The receiver utilizes only two clock phases instead of the four conventionally used in a quarter-rate clocking system. This two-clock phase system is enabled by a passive silicon photonic split and delay structure that eliminates the need for a quadrature clock phase generator and all the associated buffers. Moreover, the outputs of the receiver are demultiplexed which further helps reducing power consumption in the digital part of the system. The receiver also employs inter-stage AC coupling and is mounted on a high-speed printed circuit board (PCB). The impact of AC coupling and PCB parasitics is investigated. The functionality of the receiver is validated by high-speed optical measurements. The receiver achieves an error-free transmission (BER < 10 −12) up to a data rate of 12.5 Gb/s with an energy efficiency of 1.93 pJ/bit and sensitivity of −4 dBm from a 1 V supply.

A 22-Gb/s Time-Interleaved Low-Power Optical Receiver With a Two-Bit Integrating Front End

“…The sensitivity of the proposed system is, theoretically, 3 dB below a full-bandwidth system operating at the same data rate due to the excess insertion loss of the delay lines. Moreover, as indicated by (17), the front end boosts the sensitivity of the electronic part of the receiver by 3.8 dB when the bandwidth is 0.35× data rate in comparison with a current amplifier-based receiver and by 3 dB in comparison with the integrating front-end receiver. As a result, the sensitivity of the proposed receiver is only 2.2 and 3 dB below these systems, respectively, considering the 6-dB optical losses.…”

“…From 15, a PD with high responsivity and small junction capacitance is desirable for optimal sensitivity. Moreover, the current is integrated over a full UI (T b ) in (16) or two full UIs (2T b ) in (17) and (18), as opposed to the 0.5 T b and 0.75 T b used in resettable receiver front ends and current-amplifierbased receivers, respectively. It can also be shown that v 01 is equal to v 11 − v 10 from the three v equations, (16)- (18).…”

“…To compensate for the small value of the coupling capacitor C C , the value of R is increased, and a low-cutoff frequency of 750 kHz is maintained. It can be shown that a large value of R and a small value of C C results in a negligible noise contribution to the input-referred noise and does not affect the sensitivity of the receiver [17]. The low cutoff frequency ensures that the bit patterns [01] and [10] completely overlap, as shown in Fig.…”

“…Finally, the receiver in [17] is a 12.5 Gb/s 1.93 pJ/bit conventional full-bandwidth receiver with a sensitivity of −3.4 dBm OMA. This receiver uses a conventional commongate input stage and optical delay lines to replace clock generation.…”

“…This receiver uses a conventional commongate input stage and optical delay lines to replace clock generation. The proposed receiver achieves an all-around better performance than [17] thanks to the two-bit low-bandwidth integrating front-end.…”