Degradation mechanisms accelerated by harsh conditions (high temperature, electrical stress) can affect circuit performances. Submitted to electromagnetic interferences, aged components can become more susceptible, which stirs up questions about the safety level of the final application. Unfortunately, the impact of circuit aging on its susceptibility level remains under evaluated and is not taken into account at circuit design level. This paper presents a first attempt of a modeling methodology aiming at predicting the impact of circuit aging on the susceptibility to electromagnetic interferences. This methodology is applied to model and explain the measured variations of the susceptibility level of phase-locked loop after an accelerated-life test.
In this paper the usefulness of the nth power law MOSFET model under Hot Carrier Injection (HCI) wearout has been experimentally demonstrated. In order to do that, three types of nFET transistors have been analyzed under different HCI conditions and the nth power law MOSFET model has been extracted for each sample. The results show that the model can reproduce the MOSFET behavior under HCI wearout mechanism. Therefore, the impact of HCI on circuits can be analyzed by using the nth power law MOSFET model.
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