We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO 2 gate dielectric. The wet etch of TaSiN had a minimal impact on HfO 2 (∆EOT<1Å). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L g down to 85nm.
Effects of composition in Hf-silicate are evaluated for CMOSFET with TiN gate. Higher k value can be achieved by reducing Si content, effective to improve EOT-Jg performance. Lower Si content is also beneficial in terms of PMOS Vt variation caused by B diffusion. However, enhanced transient charge-trapping effect (TCE) is observed from Hf-silicate with low Si content, degrading electron mobility. Hf-silicate with low Si content also shows more TCE during positive bias stress at low stress bias, which is easily de-trapped. More permanent damage is observed in the Hf-silicate with high Si content due to relatively larger amount of SiO 2 portion in the film. TCE is reduced significantly when Hf-silicate scales aggressively (T physical ≤ 3nm), espcially for low Si content. For high performance application, scaled Hfsilicate with low Si content is desirable due to thinner EOT and less TCE.
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