In this paper, a new design to reduce the overhead required for fully testable PLA is proposed. This design exploits the fact that product lines in a PLA can be rearranged and grouped into few partitions. Then, some extra outputs are added, one per partition, to make the whole PLA testable. The overhead required by this design is significantly less than that of previous methods.
In this paper, the problem of determining the interconnections among component modules for topdown VLSI layout design is discussed. Two main steps, pin assignment and global routing, are attacked simultaneously. They are integrated and formulated into one special Steiner minimal tree problem.An algorithm is then presented to solve it. Also, the local resident effect of many interconnection nets on a layout is considered. A strategy based upon this effect is proposed to speed up this algorithm.
This paper proposes a new architecture for analog median filters, without the high accuracy reference voltage, high speed analog summer , and linear sawtooth wave generator , therefore it is easy to implement by VLSI technology. The features of this architecture are modular , regular, locally connected and expansible. The throughput is independent of tht window size and the hardware complexity is linearly dependent on the window size. i
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.