Performance-driven global routing based on simulated evolution

Wang, L.Y.; Liu, B.D.; Lai, Yen-Tai; Yeh, Meng-Hsin

doi:10.1109/tencon.1993.320038

Cited by 2 publications

(1 citation statement)

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“…In TIGER, the routing tree is chosen so that the timing constraint along the critical path can be satisfied, which provides greater flexibility than the net-based constraints. Similarly, the method of Wang et al [154] is also based on the path. It preferentially routing each critical synchronization path and minimizes its delay.…”

Section: ) Timing/delay-driven Routingmentioning

confidence: 99%

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

et al. 2020

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Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration (VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall chip performance. Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design. In a GR process, a Steiner Minimum Tree (SMT) algorithm can be invoked millions of times, which means that SMT algorithm has great significance for the final quality of GR. Some of the research works are surveyed in this paper to understand GR and SMT problems and to learn the available solutions. Firstly, we systematically dissect three types of subproblems in Steiner tree construction and three types of GR methods. Then, we investigate the recent progress under two new technology models. Finally, the survey concludes with a summary of possible future research directions.

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Section: ) Timing/delay-driven Routingmentioning

confidence: 99%