Simultaneous pin assignment and global wiring for custom VLSI design

Wang, L.Y.; Lai, Yen-Tai; Liu, B.D.

doi:10.1109/iscas.1991.176705

Cited by 8 publications

(3 citation statements)

References 13 publications

(5 reference statements)

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“…Ozdal & Wong (2004) and Ozdal & Wong (2006) can be regarded as the initial work on SER as they consider two pin arrays simultaneously and minimize the net ordering mismatch. There are some studies in the literature that have proposed a simultaneous pin assignment Xiang, Tang & Wong ( 2001), Wang, Lai & Liu (1991). Ozdal & Wong (2004 propose a methodology to escape the pins to boundaries in such a way that crossings are minimized in the intermediate area.…”

Section: Related Workmentioning

confidence: 99%

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Ali

Anjum

Zeeshan

2021

PeerJ Computer Science

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Simultaneous Escape Routing (SER) is the escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER in PCBs a very inefficient and tedious task and there surely is need for the automated routing algorithms. In this work, we propose network flow based optimal algorithm that uses integer linear program to solve SER problem and area routing problem in two stages. In the first stage, pins are escaped to the boundaries of pin arrays simultaneously. These escaped pins are connected with each other in the second stage. The proposed algorithm is tested for different benchmark sizes of grids and the results show that it is not only better in terms of routability but also outperforms existing state of the art algorithms in terms of time consumption. The existing algorithms either fails to achieve higher routability or have larger time complexities, whereas the proposed algorithm achieves 99.9% routability and is also independent of grid topology and component pin arrangement, which shows the superiority of proposed algorithm over the existing algorithms.

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Section: Related Workmentioning

confidence: 99%

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Ali

Anjum

Zeeshan

2021

PeerJ Computer Science

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“…[4] develops a multi-level physical hierarchy generation algorithm integrated with fast incremental global routing for directly updating and optimizing congestion. A channel connection graph was used as the global routing graph in [6], and feedthrough paths inside macrocells are allowed in the algorithm. But, none of these methods deal with routing congestion in hierarchical physical design.…”

Section: Introductionmentioning

confidence: 99%

Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel

Prasad

Kumar

2009

2009 22nd International Conference on VLSI Design

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In macrocell based SoC design, a routing plan to decongest top channel is an important step during floor planning. While previous approaches attempt at reducing congestion of chip as a whole, there is no attempt to specifically decongest top channel. We present an algorithmic approach to decongest top channel by using very few feedthroughs. Results show that compared to conventional methods, we can decongest top channel by using 20% lesser feedthrough buffers, and better top channel routing resource utilization.

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“…Hence, the pin assignment may cause difficulties in the actual global routing. A channel connection graph was used as the global routing graph in [4], and feed-through paths inside macros are also allowed in the algorithm. A channel graph was used in [3] to perform the routing and allowed block re-shaping.…”

Section: Introductionmentioning

confidence: 99%

Multilayer pin assignment for macro cell circuits

Liu

Sechen

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We present a pin-assignment algorithm based on a new multi-layer chip-level global router. Combining pin assignment and global routing has been an important approach for the pin-assignment problem. But there are many difficulties when combining the two processes. In the past, only specialized global routing methods were used in the combined process. In our pin assignment program, we use an actual global routing algorithm. To meet the requirement of pin assignment while keeping the routing quality, we dynamically adjust the weights in the routing graph during the routing stage. In addition, the multi-layer technology has introduced new challenges for the pin-assignment problem. Our algorithm can also handle the modern technology to provide pin assignment for multi-layer layouts. To our knowledge, no other pin assignment program can handle multi-layer layout. Tests on industrial circuits show that our pin-assignment algorithm is quite effective at reducing the demand for routing resources.

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Simultaneous pin assignment and global wiring for custom VLSI design

Cited by 8 publications

References 13 publications

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel

Multilayer pin assignment for macro cell circuits

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