The occurrence of errors is often thought to impede associative learning. This was tested in 2 studies, each of which involved 2 sessions. In Session 1, subjects learned foreign vocabulary (Experiment 1) or obscure English words (Experiment 2) and received 2 tests (each with corrective feedback) separated by a variable lag. Greater lags drastically reduced performance on the 2nd test. However, they dramatically improved performance in a Session-2 test given 1 day (Experiment 1) or 1 week later (Experiment 2). This pattern held even for items that elicited errors on the 1st test of Day 1. Evidently, the benefit of spacing overwhelms any possible harmful effect of producing errors. The results have clear and nonobvious implications for computer-aided instruction.

Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10−5 A/cm2 at a bias of −1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8–10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ∼3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves.

For the first time, we have successfully demonstrated the feasibility of integrating a high-permittivity ( ) gate dielectric material zirconium oxide into the MOS capacitors fabricated on pure germanium substrates. The entire fabrication process was essentially performed at room temperature with the exception of a 410 C forming gas anneal. After processing steps intended to remove the germanium native oxide interlayer between the zirconium oxide dielectric and germanium substrate, an excellent capacitance-based equivalent SiO 2 thickness (EOT) on the order of 5-8 Å and capacitance-voltage ( -) characteristics with hysteresis of 16 mV have been achieved. Additionally, excellent device yield and uniformity were possible using this low thermal budget process.

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Thermal stability of gate stack structures composed of ZrO2 gate dielectrics and silicon electrodes was investigated. The ZrO2 films were deposited by atomic layer deposition, while the polycrystalline silicon electrodes were deposited using different variants of chemical (CVD) and physical vapor deposition (PVD). Zirconium silicide formation was noted in all CVD-electroded samples after subsequent annealing treatments at temperatures above 750 °C, but not in the room temperature PVD-electroded samples, even after gate annealing at 1050 °C. The dependence of zirconium silicide formation on the Si deposition process was explained using thermodynamic arguments which explicitly include the effects of oxygen deficiency of the metal oxide films.