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-We propose a new algorithm for the performancedriven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner and does not greedily add edges as in conventional approaches. The algorithm can handle cases where the sink capacitances are different. Good results are obtained while running two to sixty times faster than three existing algorithms on practical instances.

We propose topology design of power distribution nets using a novel method for capturing the temporal characteristics of sink currents -the current compatibility graph. This graph carries information necessary for net area optimization. We propose a new algorithm for simultaneous topology design and wire sizing that can handle large designs. Our techniques result in significant area improvements on benchmark instances.

The synthesis of the power distribution network is an important problem in the layout design of VLSI systems. In this paper we propose novel methods to solve the problem of designing minimal area power distribution nets, while satisfying voltage drop and electromigration constraints. We will see that our methods significantly improve upon current techniques. We propose two novel greedy heuristics for power net design-one based on bottom-up tree construction using greedy merging and the other based on top-down linearly separable partitioning. We test the efficacy of our techniques on benchmark instances. The areas required by our methods on typical instances are significantly smaller than those obtained using previous methods.