Minimal delay interconnect design using alphabetic trees

Vittal, Ashok; Marek-Sadowska, Malgorzata

doi:10.1145/196244.196432

Cited by 31 publications

(10 citation statements)

References 17 publications

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“…Several early works [5,17] are dedicated to finding a good compromise between wire length and the maximum source-sink path length (also known as the radius). Later research efforts have directly considered delay metrics in the tree construction procedure [7,19,22,36,37,58,85]. For surveys on Steiner tree construction techniques for VLSI routing, the reader is referred to [11,16,45].…”

Section: Maze Routingmentioning

confidence: 99%

A survey on multi-net global routing for integrated circuits

Sapatnekar

2001

Integration

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This paper presents a comprehensive survey on global routing research over about the last two decades, with an emphasis on the problems of simultaneously routing multiple nets in VLSI circuits under various design styles. The survey begins with a coverage of traditional approaches such as sequential routing and rip-up-and-reroute, and then discusses multicommodity flow based methods, which have attracted a good deal of attention recently. The family of hierarchical routing techniques and several of its variants are then overviewed, in addition to other techniques such as move-based heuristics and iterative deletion. While many traditional techniques focus on the conventional objective of managing congestion, newer objectives have come into play with the advances in VLSI technology. Specifically, the focus of global routing has shifted so that it is important to augment the congestion objective with metrics for timing and crosstalk. In the later part of this paper, we summarize the recent progress in these directions. Finally, the survey concludes with a summary of possible future research directions.

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Section: Maze Routingmentioning

confidence: 99%

A survey on multi-net global routing for integrated circuits

Sapatnekar

2001

Integration

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“…Nevertheless, the routing trees it produces are often of high quality. The work of Vittal and MarekSadowska [16] used the abstraction of Alphabetic Trees to This work was supported in part by Grants from the NSF project MIP-9315794 and California MICRO program.…”

Section: Introductionmentioning

confidence: 99%

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Lillis

Cheng

Lin

et al. 1996

Proceedings of the 33rd Annual Conference on Design Automation Conference - DAC '96

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We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure f r om previous approaches in that we derive an explicit area/delay tradeo curve. We achieve this goal by limiting the solution space to the set of topologies induced b y a p ermutation on the sinks of the net. This constraint allows ecient identication of optimal solutions while still providing a rich solution space. We also incorporate simultaneous wire sizing. Our technique consistently p r o duces topologies equalling the performance o f previous approaches with substantially less area overhead.

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“…A timing optimum interconnect tree may not be a RSMT on the Hanan grid, 2 since Elmore delay to a sink can be decreased by non-Hanan sliding [10,15].…”

Section: Slidingmentioning

confidence: 99%

“…and arborescences (e.g., A-Tree [7]), or shallow-light tree 1 [3] (e.g., AHHK [2], BPRIM and BRBC [6]) are insensitive to electrical parameters (e.g., driver strength, sink load capacitance, required-arrival times) and thus give the same results over all technologies, pin loads, driver strengths, etc. Elmore-delay-based timing optimization heuristics (e.g., C-Tree [1], ERT, SERT, SERT-C [4], PER-Steiner [5] and Alphabetic tree [15]) do not guarantee timing performance: e.g., C-Tree solutions are limited in 5 empirical AHHK-over-SMT tree topologies; and PER-Steiner constructs shortest paths to pre-identified critical sinks before further improvements. Dynamic programming approaches (e.g., BA-Tree [14], MBA-Tree, RMP [8], P-Tree [13] and S-Tree [11]) can achieve optimum area or timing performance, and can extend to address such functionality as simultaneous buffering, use of buffer stations, and routing obstacle avoidance.…”

Section: Introductionmentioning

confidence: 99%

Q-Tree: a new iterative improvement approach for buffered interconnect optimization

Kahng

Liu

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

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The "chicken-egg" dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as Hanan grafting and non-Hanan sliding, and reveal generally negligible contribution of non-Hanan sliding. We propose a greedy iterative interconnect timing optimization algorithm called Q-Tree. Our experimental results show that Q-Tree starting with Steiner minimum tree topologies achieves better timing performance than C-Tree [1], PER-Steiner [5] and BA-Tree [14] algorithms. Also, executing Q-Tree starting with BA-Tree or P-Tree [13] topologies can achieve better timing performance, especially, with shorter wires and fewer buffers. In general, Q-Tree can be applied to any interconnect tree for further timing performance improvement, with practical instance sizes and easily-extended functionality -e.g., with buffer station and routing obstacle avoidance consideration.

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Minimal delay interconnect design using alphabetic trees

Cited by 31 publications

References 17 publications

A survey on multi-net global routing for integrated circuits

A survey on multi-net global routing for integrated circuits

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Q-Tree: a new iterative improvement approach for buffered interconnect optimization

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