Power optimal buffered clock tree design

Vittal, Ashok; Marek-Sadowska, Malgorzata

doi:10.1145/217474.217577

Cited by 36 publications

(16 citation statements)

References 21 publications

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“…The rationale is that instead of increasing wire widths and lengths to reduce the skew which will result in increased power dissipation, one can use a balanced buffer insertion scheme to partition a large clock tree into a small number of subtrees with minimum wire widths. In [163] a technique for low power clock synthesis that simultaneously inserts buffers and generates the clock tree topology is presented. The main advantage of this approach is that by judicious buffer insertion, one can reduce the total wire length needed to achieve zero-skew clock tree.…”

Section: Clock Tree Generationmentioning

confidence: 99%

Power minimization in IC design

Pedram

1996

ACM Trans. Des. Autom. Electron. Syst.

392

135

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Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing design-ers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

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Section: Clock Tree Generationmentioning

confidence: 99%

Power minimization in IC design

Pedram

1996

ACM Trans. Des. Autom. Electron. Syst.

392

135

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“…Many previous works [15][16][17][18] place buffers of the same size at nodes of the same level in the clock tree for two reasons: (1) zero skew routing generally results in a balanced tree; (2) this level by level buffering scheme can reduce the effect of inter-die process variations. However, this strategy is not applicable for non-zero skew routing which may generate unbalanced trees.…”

Section: Introductionmentioning

confidence: 99%

Buffered clock tree for high quality IC design

Chaturvedi

SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)

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“…Recently, Minz, Zhao, and Lim [15] proposed a thermal-aware clock tree synthesis algorithm, called BURITO, where it extended the existing 2D clock tree synthesis algorithms, namely, it performed 3D tree topology generation by extending MMM (Method of Means and Medians) in [16], embedding tree by using DME (Deferred-Merge Embedding) in [22], inserting buffers using the work in [17], and finally relocating merging points to balance clock skew under thermal variations by extending the merging diamond concept proposed in TACO [18]. To our knowledge, BURITO is the only work that addresses the clock tree synthesis problem in 3D ICs, but the work is limited to two layer face-to-face wafer bonded 3D ICs only.…”

Section: Introductionmentioning

confidence: 99%

“…Bounded skew clock routing algorithms were developed by [27,28,29,30]. Moreover, power optimal clock buffer insertion and temperature aware clock tree optimization techniques were developed in [17] and [18], respectively, while clock buffer polarity assignment techniques were proposed for power noise reduction by [31,32,33,34]. In the 2D clock tree synthesis researches, the DME [22,23,24,25] algorithm constructs a wirelength optimal zero skew clock tree for a given tree topology under the linear delay model, and a suboptimal clock tree under the Elmore delay model [19,20,21].…”

Section: Introductionmentioning

confidence: 99%

Clock tree embedding for 3D ICs

Kim,

Kim

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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This paper addresses a fundamental problem of zero skew clock tree embedding problem in 3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree embedding problem in 3D ICs for a given tree topology. The primary objective is to minimize the cost of TSVs together with finding embedding layers and the secondary objective is to minimize the cost of wirelength. We show that ZCTE-3D solves the problem optimally in polynomial time under the linear delay model, while it solves the problem suboptimally under the Elmore delay model. We also propose an effective 3D clock tree synthesis flow by integrating a multi-layer tree topology generation algorithm, called MMM-3D, into ZCTE-3D. Through an extensive exploitation of ZCTE-3D in experiments, we have analyzed the relation between the number of TSVs, the total wirelength, and tree topology. When compared with the results produced by the previous 3D clock tree synthesis algorithm BURITO, experimental results show that ZCTE-3D uses on average 10% less number of TSVs with similar wirelength and delay for the same tree topologies. Furthermore, by generating tree topologies with MMM-3D, we are able to reduce the number of TSVs by 10% on average even with 4% shorter wirelength and 2% reduced delay.

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Power optimal buffered clock tree design

Cited by 36 publications

References 21 publications

Power minimization in IC design

Power minimization in IC design

Buffered clock tree for high quality IC design

Clock tree embedding for 3D ICs

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