Power minimization in IC design

Pedram, Massoud

doi:10.1145/225871.225877

Cited by 392 publications

(138 citation statements)

References 121 publications

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“…(For more details on dynamic and static power modeling, see Chandrakasan and Brodersen 1995, Pedram 1996 For the moment, we are assuming that power supply voltage and clock frequency (which scales the activity frequencies, assuming given activity factors) are constant. But if clock frequency or supply voltage are varied, the two components of the total power vary in different ways.…”

Section: Audience and Goalsmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

153

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Section: Audience and Goalsmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

153

146

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show abstract

“…Power dissipation in CMOS combinational circuits arises from the following sources [17,27]: dynamic power dissipation due to switching current from charging and discharging the parasitic capacitances, dynamic power dissipation due to short-circuit current when both n-channel and p-channel transistors are momentarily on at the same time and static power dissipation due to leakage current and subthreshold current.…”

Section: Estimation Of Weighted Maximum Switching Activitymentioning

confidence: 99%

“…Therefore an estimate of the maximum current during power-up is essential in designing reliable and high performance CMOS combinational circuits. Unlike the maximum switching current which depends on two input vectors [17], maximum wake-up current depends only on one input vector. Assume that we are using a PMOS sleep transistor and all internal nodes are fully discharged during sleep mode.…”

Section: Maximum Power-up Current Estimationmentioning

confidence: 99%

“…Excessive power dissipation may cause run-time errors and device destruction due to overheating, while excessive instantaneous current through the power and ground (P&G) nets may result in performance degradation due to large voltage drops along the P&G nets, and circuit failures due to electromigration. Hence, the estimation of maximum possible power in VLSI circuits is essential for determining the appropriate packaging and cooling techniques and for optimizing the power and ground routing networks [14][15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

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Using SAT-based techniques in power estimation

Sagahyroon

Aloul

2007

Microelectronics Journal

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Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the successful deployment of SAT technology in a wide range of applications domains, and particularly in electronic design automation (EDA). SAT is increasingly being used as the underlying model for a number of applications in EDA. This paper describes how to formulate two problems in power estimation of CMOS combinational circuits as SAT problems or 0-1 integer linear programming (ILP). In these circuits, it was proven that maximizing dissipation is equivalent to maximizing gate output activity, appropriately weighted to account for differing load capacitances. The first problem in this work deals with identifying an input vector pair that maximizes the weighted circuit activity. In the second application we attempt to find an estimate for the maximum power-up current in circuits where power cut-off or gating techniques are used to reduce leakage current. Both problems were successfully formulated as SAT problems. SAT-Based and generic Integer Linear Programming (ILP) solvers are then used to find a solution. The experimental results obtained on a large number of benchmark circuits provide promising evidence that the proposed complete approach is both viable and useful and outperforms the random approach. r

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“…Low power design targeting minimum switched-capacitance has made significant progress in recent years. [2] Researchers and designers however remain interested in developing logic elements that operate based on a different type of energy conversion, i.e., one that minimizes the conversion of electric energy to heat.…”

Section: Introductionmentioning

confidence: 99%

Analysis of power-clocked CMOS with application to the design of energy-recovery circuits

Pedram

Wu²

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

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Power minimization in IC design

Cited by 392 publications

References 121 publications

Digital Circuit Optimization via Geometric Programming

Digital Circuit Optimization via Geometric Programming

Using SAT-based techniques in power estimation

Analysis of power-clocked CMOS with application to the design of energy-recovery circuits

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