We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-on-Chip (SOC) and automatic generation of a retargetable compiler/simulator toolkit. Key features of our language-driven design methodology include: a mixed behavioral/structural representation supporting a natural specification of the architecture; explicit specification of the memory subsystem allowing novel memory organizations and hierarchies; clean syntax and ease of modification supporting architectural exploration; a single specification supporting consistency and completeness checking of the architecture; and efficient specification of architectural resource constraints allowing extraction of detailed reservation tables for compiler scheduling. We illustrate key features of EXPRESSION through simple examples and demonstrate its efficacy in supporting exploration and automatic software toolkit generation for an embedded SOC codesign flow.

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Reservation Tables (RTs)

Modem Embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memories. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an tntegmted software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPS (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space ezploration (for performance, power and cost constraints), as well as high-quality software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and ezplomtion of SOC architectures. The second part of the paper focuses on approaches to software toolkit genemtion that automatically produce the software infrostructure (e.g., compilers, simulators, debuggers) which will enable true hardware/software codesign of these emerging embedded SOCs. t This work is supported in part by grants from NSF (MIP-4 Research at UCI is supported by JSPS postdoctoral fel-9708067 and ONR (N00014-951-1348). lowships for research abroad.

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Reservation Tables (RTs)

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For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32-bit) Instruction Set, and a narrow, space-efficient (usually 16-bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the routine-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a compilation framework for such dual instruction sets, which uses a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage of both Instruction Sets. We demonstrate consistent and improved code size reduction (on average 22%), for the MIPS 32/16 bit ISA. We also show that the code compression obtained by this "dual instruction set" technique is heavily dependent on the application characteristics and the narrow Instruction Set itself.