Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)

Abstract

For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32-bit) Instruction Set, and a narrow, space-efficient (usually 16-bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the routine-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a compilation framework for such dual instruction sets, which uses a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage of both Instruction Sets. We demonstrate consistent and improved code size reduction (on average 22%), for the MIPS 32/16 bit ISA. We also show that the code compression obtained by this "dual instruction set" technique is heavily dependent on the application characteristics and the narrow Instruction Set itself.

Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs

“…The code for an rISA processor contains both normal and rISA instructions, as shown in Figure 7, from Shrivastava et al [2006]. The fetch mechanism of the processor is oblivious to the processor's mode of execution regardless of the processor executing an rISA or normal instruction, the instruction fetch of the processor remains unchanged.…”

SHRINK: Reducing the ISA complexity via instruction recycling

“…The prefixes expand the opcode space to accommodate new instructions, but increase the length of new instructions relative to that of old instructions. The alternative processor modes enable the reinterpretation of 32-bit instructions in the context of 64-bit programs [16,28], but add complexity to the processor design. Conversely, the IBM POWER ISA admits some loss of backward compatibility in trade for cost and performance optimizations.…”

An XOR‐based parameterization for instruction register files

“…MIPS16 instruction set includes a fixed subset of original MIPS instructions. Shrivastava et al reported that the code size of the MIPS32/16 program was reduced by 22% on average with a careful selection of instructions. Similarly, some of recent ARM processors have an additional 16‐ and 32‐bit ISA called Thumb‐2 .…”

“…Similarly, some of recent ARM processors have an additional 16‐ and 32‐bit ISA called Thumb‐2 . However, the efficiency of such dual‐ISA designs is heavily dependent on the application : if most of the executed instructions are not included in the subset, they must be executed by the traditional instructions and thus the number of instruction fetches is almost unchanged. CISC processors have variable‐length ISAs to achieve a high code density and an efficient use of instruction caches, though their decoder circuits are much more complicated than those of RISC.…”