V-SAT: a visual specification and analysis tool for system-on-chip exploration

Khare, Asheesh; Savoiu, Nick; Halambi, Ashok; Grun, Peter; Dutt, Nikil; Nicolau, Alex

doi:10.1109/eurmic.1999.794466

Cited by 23 publications

(4 citation statements)

References 8 publications

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“…The ADL has been used by the retargetable compiler (EXPRESS [26]) and simulator (SIMPRESS [27]) generation framework. The framework also supports a graphical user interface (GUI) and can be used for design space exploration of programmable architectures consisting of processor cores, coprocessors and memories.…”

Section: Expressionmentioning

confidence: 99%

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Processor Description Languages

Mishra¹,

Dutt²

2008

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Embedded systems present a tremendous opportunity to customise designs by exploiting the application behaviour. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures. Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design constraints such as area, power and performance. The ADL is used to specify programmable embedded systems, including processor, coprocessor and memory architectures. The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures. The paper surveys the existing ADLs in terms of (a) the inherent features of the languages and (b) the methodologies they support to enable simulation, compilation, synthesis, test generation and validation of programmable embedded systems. It concludes with a discussion of the relative merits and demerits of the existing ADLs and expected features of future ADLs.

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Section: Expressionmentioning

confidence: 99%

“…Almost all commercially available simulators are interpretive. Examples of research interpretive retargetable simulators include SIMPRESS [27] using EXPRESSION and GENSIM=XSIM [21] using ISDL.…”

Section: Simulatorsmentioning

confidence: 99%

Processor Description Languages

Mishra¹,

Dutt²

2008

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“…Also, by automatically generating the conflict information, we avoid redundancy in the input processor specification. In our approach, the same architectural specification is used to generate both a structural simulator SIMPRESS [13], as well as the RTs required by our optimizing compiler EXPRESS.…”

Section: Related Workmentioning

confidence: 99%

RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions

Grun

Halambi

Dutt

et al. 2003

IEEE Trans. VLSI Syst.

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“…Esta restrição também se aplicam a ISDL [24]. EXPRESSION permite a modelagem de processadores com pipeline com precisão de ciclos e de bits [36]. A linguagem LISA permite retargeting de simuladores com precisão de ciclos para microcontroladores e DSPs [52,53].…”

Section: Simulação Com Precisão De Ciclosunclassified

Simulação compilada para arquiteturas descritivas em ArchC

Bartholomeu¹,

Azevedo²

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The simulator is one of the most important tools to design a new computer architecture. It has many advantages, the most important are flexibility and low cost. The first simulators were created manually, which was an error-prone practice. Nowadays, Architecture Description Languages (ADLs) simplifies the generation of these tools.This work focus on the research of new fast simulation techniques using the ArchC ADL. Beginning from the state-of-art in this area, the compiled simulation, is was possible to speed-up the instruction set simulation performance even higher. Two optimizations were proposed. The first one simulates basic blocks atomically, without any condition test between instructions, and speed-up the simulation by 70% in average. The second optimization anticipates the majority of target address calculation for jump instructions, allowing the flow control to be done by the simulator. This second optimization is an improvement to the first one, and provides an speed-up of 180% in average.Besides the research of fast simulation techniques, a methodology was created to allow architecture simulators to interact with the host machine, which makes it possible, for example, to access local files and take options from command-line. Also, an interface were defined to access external data which allows a propotype imlementation of a multiprocessor architecture simulator. This interface will be integrated to ArchC to achieve co-simulation capability for generic blocks described in SystemC.x AgradecimentosAgradeço a Deus pela inspiração para fazer este trabalho. Agradeço principalmente a meus pais Luiz e Eliane e a meu irmão Ricardo, por eles sempre me incentivarem durante estes anos.Agradeço ao meu orientador, Rodolfo Azevedo, e ao meu co-orientador, Guido Araújo, pelas trocas de idéias e pela ajuda para definir o tema de pesquisa. Agradeço também meu primeiro orientador, Ricardo Pannain, pela ajuda no meu primeiro ano em Campinas e o Sandro Rigo, por ter iniciado os trabalhos com ArchC.Agradeço ainda as agências financiadoras que proporcionaram bolsa de estudos para eu me manter financeiramente. Obtive bolsa da CAPES no primeiro ano e da FAPESP (01/09424-0) nos anos seguintes, fechando o último semestre com uma bolsa BIPED.São muitas as pessoas sem as quais esta Tese não seria possível. Vou tentar me lembrar da maioria delas aqui. É muito provável que eu esqueça alguém, portanto peço a meus amigos de jornada que não se sintam preteridos por não estarem aqui.Agradeço: a todas as gerações dos Pistolinhas (Triste, Zeh+Carmem, Baiano, Cláudio Guido, Daniel, Cleo), por estarem sempre presentes e por me concederem o título Pistolinha Honorário; aos amigos do LSC (Thiago,

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V-SAT: a visual specification and analysis tool for system-on-chip exploration

Cited by 23 publications

References 8 publications

Processor Description Languages

Processor Description Languages

RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions

Simulação compilada para arquiteturas descritivas em ArchC

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