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With the ever-growing demand for renewable energy sources, energy harvesting from natural resources has gained much attention. Energy sources such as heat and mechanical motion could be easily harvested based on pyroelectric, thermoelectric, and piezoelectric effects. The energy harvested from otherwise wasted energy in the environment can be utilized in self-powered micro and nano devices, and wearable electronics, which required only µW-mW power. This article reviews pyroelectric energy harvesting with an emphasis on recent developments in pyroelectric energy harvesting and devices at micro/nanoscale. Recent developments are presented and future challenges and opportunities for more efficient materials and devices with higher energy conversion efficiency are also discussed.

An accurate measurement of the thermophysical properties of freestanding thin films is essential for modeling and predicting thermal performance of microsystems. This paper presents a method for simultaneous measurement of in-plane thermal conductivity and heat capacity of freestanding thin films based on the thermal response to a sinusoidal electric current. An analytical model for the temperature response of a freestanding thin film to a sinusoidal heating current passing through a metal heater patterned on top of the thin film is derived. Freestanding thin-film samples of silicon nitride and nickel titanium (NiTi), a shape memory alloy, are microfabricated and characterized. The thermal conductivity of thin-film NiTi, which increases linearly between 243K and 313K, is 40% lower than the bulk value at room temperature. The heat capacity of NiTi also increases linearly with temperature in the low temperature phase and is nearly constant above 280K. The measurement technique developed in this work is expected to contribute to an accurate thermal property measurement of thin-film materials. Thermophysical measurements on NiTi presented in this work are expected to aid in an accurate thermal modeling of microdevices based on the shape memory effect.

This paper reports results from electrical and thermal conduction measurements carried out on the DNA-gold composite for which the overall conduction is shown to be dominated by the DNA rather than the discontinuous gold coatings. The electrical and thermal conductivities of the composite were about 14 S/cm and 150 W/(m K) at room temperature, respectively. The resulting value of 3.6 x 10(-4) W ohms/K(2) for the Lorentz number indicates that thermal transport in the DNA is phonon-dominated and that the molecular vibrations play a key role in both electrical and thermal conduction processes of DNA molecules.

Thermal runaway is a well-known safety concern in Li-ion cells. Methods to predict and prevent thermal runaway are critically needed for enhanced safety and performance. While much work has been done on understanding the kinetics of various heat generation processes during thermal runaway, relatively lesser work exists on understanding how heat removal from the cell influences thermal runaway. Through a unified analysis of heat generation and heat removal, this paper derives and experimentally validates a non-dimensional parameter whose value governs whether or not thermal runaway will occur in a Li-ion cell. The parameter comprises contributions from thermal transport within and outside the cell, as well as the temperature dependence of heat generation rate. Experimental data using a 26650 thermal test cell are in good agreement with the model, and demonstrate the dependence of thermal runaway on various thermal transport and heat generation parameters. This parameter is used to predict the thermal design space in which the cell will or will not experience thermal runaway. By combining all thermal processes contributing to thermal runaway in a single parameter, this work contributes

Three-dimensional (3D) interconnection technology offers several electrical advantages, including reduced signal delay, reduced interconnect power, and design flexibility. 3D integration relies on through-silicon vias (TSVs) and the bonding of multiple active layers to stack several die or wafers containing integrated circuits (ICs) and provide direct electrical interconnection between the stacked strata. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in stacked 3D ICs are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multidie stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of a single-valued junction-to-air thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package and heat sink thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the multidie stack. The improvement required in package and heat sink thermal resistances for a 3D logic-on-memory implementation to be thermally feasible is quantified. An increase in maximum temperature in a 3D IC compared to an equivalent system-in-package (SiP) is predicted. This increase is found to be mainly due to the reduced chip footprint. The increased memory die temperature in case of memory-on-logic integration compared to a SiP implementation is identified to be a significant thermal management challenge in the future. The results presented in this paper may be useful in the development of thermal design guidelines for 3D ICs, which are expected to help maximize the electrical benefits of 3D technology without exacerbating thermal management issues when implemented in early-stage electrical design and layout tools.Index Terms-Die stacking, electrical-thermal co-design, junction-to-air thermal resistance, three-dimensional (3D) integrated circuits (ICs), through-silicon via (TSV).