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This work was supported in part by the European Social Funds through ''CyPhiS-the program of modern Ph.D. studies in the field of cyber-physical systems'' under Project POWR.03.02.00-00-I007/17-00, and in part by the Ministry of Science and Higher Education under Grant BKM-573/RAu-11/2022 and Grant BK-246/RAu-11/2022.

The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8-12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

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The paper describes the high level abstract SystemC model of the multitask real time system. The authors put their main effort to obtain the highly time predictable system, The time predictability of real time embedded, electronic systems is identified and a concise survey of various approaches to the problem are given. The architecture of a single pipeline processor core with thread interleaving mechanism is emphasized. The scheduling algorithms that enable optimal utilization of the processing units are illustrated on examples. The main memory access control unit and the original memory system organization are described. Many simulation experiments conducted with single and multi-core system architecture implementation, allow obtaining results that prove advantages of the presented model.

The paper concerns the problem of Boolean satisfiability checking, which is recognized as one of the most important issues in the field of modern digital electronic system verification and design. The paper analyzes different strategies and scenarios of the proving process, and presents a modified and extended version of the author's FUDASAT algorithm. The original FUDASAT methodology is an intuitive approach that employs a commonsense reasoning methodology. The main objective of the work is to investigate the SAT-solving process and try to formulate a set of rules controlling the reasoning process of the FUDASAT inference engine. In comparison with the author's previous works, the paper introduces new mechanisms: hypergraph analysis, multiple variable assignments and search space pruning algorithms. The approach considers only 3-SAT class functions, although a generalization of the method is discussed as well. The presented approach has been tested on various benchmarks and compared with the original pure FUDASAT algorithm as well as with other algorithms known from the literature. Finally, the benefits of the proposed SAT solving technique are summarized.