A Heuristic Fault Dictionary Reduction Methodology

Pułka, Andrzej

doi:10.1109/icecs.2007.4511190

Cited by 2 publications

(10 citation statements)

References 14 publications

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“…The SALTO algorithm has produced optimal results in 10 ms! [2]. Then other benchmark examples [4,8] have been tested.…”

Section: The Experimental Tests Of the Algorithmsmentioning

confidence: 99%

“…Ordered Nodes: [7,5,6,2,1,4,3] New order of faults after the sorting procedure run: [2,7,13,9,11,4,12,10,14,5,8,1,3,6] Numbers of selected measuring nodes: [7]. List of remaining faults: [2,4,5,6,8,9,12,13,14] Total number of unrecognized faults equals 9 Numbers of selected measuring nodes: [5,7] List of remaining faults: [2,4,5,6,9,12,13,14] Total number of unrecognized faults equals 8 End of Node search. Selected nodes: [5,7] COSMO algorithm started Node nr: 1 has to be added.…”

Section: Salto Algorithm Startedmentioning

confidence: 99%

“…In case of state-variable filter ( Fig. 2 and Table 1), after the sorting phase we obtain the following order of measuring nodes: [7,5,6,2,1,4,3] and the faults are sorted in the following order {2, 7, 13, 9, 11, 4, 12, 10, 14, 5, 8, 1, 3, 6} (these numbers correspond to row numbers of Table 1). Step 6 of the SALTO procedure examines the first (the most significant) node from the list -node #7.…”

Section: Salto Algorithm Startedmentioning

confidence: 99%

“…This node can uniquely separate 5 faults, i.e. the 'singleton set' SALTO algorithm started Ordered Nodes: [8,6,4,7,5,14,13,12,11,10,9,3,2,1] Numbers of selected measuring nodes: [4] List of remaining faults: [1,2,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,25,26,28,29,30,31] Total number of unrecognized faults equals 27 Numbers of selected measuring nodes: [2,4] List of remaining faults: [1,4,6,7,8,9,10,…”

Section: Salto Algorithm Startedmentioning

confidence: 99%

“…The paper addresses the technique of proper (optimal) selection of the tests points, which is very important during the design process. The section 2 explains the motivation of the work and briefly recalls the background of testing methodologies based on a fault dictionaries; section 3 introduces two searching algorithms: SALTO [2] and COSMO (a modified and extended version of [3]) and an inference environment of the expert system in PROLOG; section 4 presents benchmark examples [4] and makes a generalization the methodology to complex devices; section 5 describes the implementation and the inference engine, and section 6 concludes the paper and emphasizes the benefits of the proposed approach.…”

Section: Introductionmentioning

confidence: 99%

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Two Heuristic Algorithms for Test Point Selection in Analog Circuit Diagnoses

Pułka¹

2011

Metrology and Measurement Systems

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The paper presents a heuristic approach to the problem of analog circuit diagnosis. Different optimization techniques in the field of test point selection are discussed. Two new algorithms: SALTO and COSMO have been introduced. Both searching procedures have been implemented in a form of the expert system in PROLOG language. The proposed methodologies have been exemplified on benchmark circuits. The obtained results have been compared to the others achieved by different approaches in the field and the benefits of the proposed methodology have been emphasized. The inference engine of the heuristic algorithms has been presented and the expert system knowledge-base construction discussed.

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“…The SALTO algorithm has produced optimal results in 10 ms! [2]. Then other benchmark examples [4,8] have been tested.…”

Section: The Experimental Tests Of the Algorithmsmentioning

confidence: 99%

Section: Salto Algorithm Startedmentioning

confidence: 99%

Section: Salto Algorithm Startedmentioning

confidence: 99%

Section: Salto Algorithm Startedmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Two Heuristic Algorithms for Test Point Selection in Analog Circuit Diagnoses

Pułka¹

2011

Metrology and Measurement Systems

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A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

et al. 2018

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Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T E) and the Yield Loss (Y L) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique. Keywords Analog/RF test • SVM classification • Neural Network classification • BIST evaluation 1 Introduction The test is a very important notion in the field of the validation step of analog circuit design. It is the way to confirm whether a circuit under test (CUT) satisfies all functional specifications that represent its performance parameters. Since there are no manufactured circuits at the design stage, test errors can only be

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A Heuristic Fault Dictionary Reduction Methodology

Cited by 2 publications

References 14 publications

Two Heuristic Algorithms for Test Point Selection in Analog Circuit Diagnoses

Two Heuristic Algorithms for Test Point Selection in Analog Circuit Diagnoses

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

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