Dynamic Rescheduling of Tasks in Time Predictable Embedded Systems

Pułka, Andrzej; Milik, Adam

doi:10.3182/20120523-3-cz-3015.00058

Cited by 7 publications

(19 citation statements)

References 7 publications

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“…(Lee and Messerchmitt, 1987) proposed a technique based on interleaved pipeline, which allows effectively eliminating data and control hazards in pipeline processing. This idea was extended by others (Edwards et al, 2009), (Pułka and Milik, 2012). One of the key issue of the multitask systems that may introduce unpredictability is the organization of the memory system.…”

Section: The Survey Of Related Workmentioning

confidence: 96%

“…The main function of this instruction is to keep control over elapsed time of the execution of defined code fragment (task). The PRET idea (Liu, 2012) inspired many researchers and various approaches based on software (PRET-C - Andalam et al, 2014), (Broman et al, 2013), (Schoeberl, 2008) as well as hardware based solutions (Cazorla et al, 2006), (Edwards et al, 2009), (Pułka and Milik, 2012), (Alhammad and Pellizzioni, 2014). To develop predictable hardware platforms.…”

Section: The Survey Of Related Workmentioning

confidence: 99%

“…Some papers deal with this problem: discuss the application of scratchpad memories (SPM) to avoid cache hit/miss problems; (Reineke et al, 2011) considers architecture with DRAM predictable controller useful when the program does not fit to SPM. The presented work is based on the previous structure of PRET architecture with dynamically rescheduled system (Pułka and Milik, 2012). New, high level approach introduces new structure of memory system.…”

Section: The Survey Of Related Workmentioning

confidence: 99%

“…New, high level approach introduces new structure of memory system. Moreover this SystemC based model is more flexible than hardware synthesizable PRET model (Pułka and Milik, 2012), and allows simulating multi-core applications and verifying different system configurations. Figure 2 introduces the structure of a pipeline processing unit -PRET processor architecture.…”

Section: The Survey Of Related Workmentioning

confidence: 99%

“…The presented approach deals with the problem of timing predictability of real time systems. In the previous work (Pułka and Milik, 2012) the hardware solution for a single-core system was developed, while in the presented work the high-level SystemC analysis of the multithreading scheduling mechanism with the multi-core extension is analyzed.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

High Level Model of Time Predictable Multitask Control Unit

2015

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The paper describes the high level abstract SystemC model of the multitask real time system. The authors put their main effort to obtain the highly time predictable system, The time predictability of real time embedded, electronic systems is identified and a concise survey of various approaches to the problem are given. The architecture of a single pipeline processor core with thread interleaving mechanism is emphasized. The scheduling algorithms that enable optimal utilization of the processing units are illustrated on examples. The main memory access control unit and the original memory system organization are described. Many simulation experiments conducted with single and multi-core system architecture implementation, allow obtaining results that prove advantages of the presented model.

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Section: The Survey Of Related Workmentioning

confidence: 96%

Section: The Survey Of Related Workmentioning

confidence: 99%

Section: The Survey Of Related Workmentioning

confidence: 99%

Section: The Survey Of Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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High Level Model of Time Predictable Multitask Control Unit

2015

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Synthesis of self-adaptable energy aware software for heterogeneous multicore embedded systems

Deniziak

Ciopinski

2021

Microelectronics Reliability

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Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Antolak

Pułka

2020

IET Circuits, Devices & Systems

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The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8-12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

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Dynamic Rescheduling of Tasks in Time Predictable Embedded Systems

Cited by 7 publications

References 7 publications

High Level Model of Time Predictable Multitask Control Unit

High Level Model of Time Predictable Multitask Control Unit

Synthesis of self-adaptable energy aware software for heterogeneous multicore embedded systems

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

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