High Level Model of Time Predictable Multitask Control Unit

Golly, Lukasz; Milik, Adam; Pułka, Andrzej

doi:10.1016/j.ifacol.2015.07.059

Cited by 6 publications

(10 citation statements)

References 12 publications

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“…Other investigations are carried out towards finding the detailed solution in the selected software [16][17][18][19] or hardware [4,5,15,[20][21][22] aspects. MA operations that are responsible for a generation of the greatest amount of 'unpredictability' are addressed in many works [1,3,7,8,16,20,23]. For example, problems of concurrent evaluation of many tasks, multiple threads and parallel processing realised on simultaneous multithreaded processors are examined in [4].…”

Section: Related Workmentioning

confidence: 99%

“…In a real‐time‐predictable system unlike in a general‐purpose multi‐core architecture we usually avoid caches [3, 5, 6, 7, 11] or maximally reduce their impact on the system behaviour [1, 21]. The contemporary multi‐core architectures that contain memory systems based on L1, L2 and recently L3 (last level cache) caches, although very efficient, introduce a lot of unpredictability.…”

Section: Our Core Architecturementioning

confidence: 99%

“…The presented structure of the core is based on the idea of thread interleaving [10] and the replication of register files [7, 11]. As in the Berkeley PRET architecture (the memory wheel) [11], the communication in our system is based on the TDMA model, but in our opinion, the presented solution is more efficient.…”

Section: Comparison With Other Workmentioning

confidence: 99%

“…First works were dedicated to predictable architecture investigations [6]. Then, we presented a more abstract approach based on SystemC models [7, 8].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Antolak

Pułka

2020

IET Circuits, Devices & Systems

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The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8-12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

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Section: Related Workmentioning

confidence: 99%

Section: Our Core Architecturementioning

confidence: 99%

Section: Comparison With Other Workmentioning

confidence: 99%

“…First works were dedicated to predictable architecture investigations [6]. Then, we presented a more abstract approach based on SystemC models [7, 8].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Antolak

Pułka

2020

IET Circuits, Devices & Systems

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“…The main effort has been toward the minimization of the total energy consumed by the system. All investigations and practical experiments have been carried out on original architecture, developed in the Department of Electronics, Electrical Engineering and Microelectronics (formerly, the Institute of Electronics) [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Antolak

Pułka

2022

Applied Sciences

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The paper concerns research on electronics-embedded safety systems. The authors focus on the optimization of the energy consumed by multitasking real-time systems. A new flexible and reconfigurable multi-core architecture based on pipeline processing is proposed. The presented solution uses thread-interleaving mechanisms that allow avoiding hazards and minimizing unpredictability. The proposed architecture is compared with the classical solutions consisting of many processors and based on the scheme using one processor per single task. Energy-efficient task mapping is analyzed and a design methodology, based on minimizing the number of active and utilized resources, is proposed. New techniques for energy optimization are proposed, mainly, clock gating and switching-resources blocking. The authors investigate two main factors of the system: setting the processing frequency, and gating techniques; the latter are used under the assumption that the system meets the requirements of time predictability. The energy consumed by the system is reduced. Theoretical considerations are verified by many experiments of the system's implementation in an FPGA structure. The set of tasks tested consists of programs that implement Mälardalen WCET benchmark algorithms. The tested scenarios are divided into periodic and non-periodic execution schemes. The obtained results show that it is possible to reduce the dynamic energy consumed by real-time applications' meeting their other requirements.

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Energy-Efficient Task Scheduling in Design of Multithread Time Predictable Real-Time Systems

Antolak¹,

Pułka

2021

IEEE Access

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High Level Model of Time Predictable Multitask Control Unit

Cited by 6 publications

References 12 publications

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Energy-Efficient Task Scheduling in Design of Multithread Time Predictable Real-Time Systems

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