Digitization is at the center of fourth industrial revolution (4IR) with previously analog systems being digitized through an analog-to-digital converter. In addition, 4IR applications such as fifth generation (5G) Cellular Networks Technology and Cognitive Electronic Warfare (EW) at some point interface digitally through an analog-to-digital converter. Efficient use of digital resources such as memory, largely depends on the signal sampling design of analog-to-digital converters. Existing even order sampling has been found to perform better than traditional sampling techniques. Research on the efficiency of a digital interface with a 4IR platform is still in its infancy. This paper presents a performance study of three sampling techniques: the proposed new and novel odd/even order sampling architecture, existing Mod-∆, and traditional 1st order delta-sigma, to address this. Step-size signal-to-noise (SNR), dynamic range, and sampling frequency are also studied. It was found that the proposed new and novel odd/even order sampling achieved an SNR performance of 6 dB in comparison to 18 dB for Mod-∆. Sampling frequency findings indicated that the proposed new and novel odd/even order sampling achieved a sampling frequency of 2 kHz in comparison to 8 kHz from a traditional 1st order sigma-delta. Dynamic range findings indicated that the proposed odd/even order sampling has achieved a dynamic range of 1.088 volts/ms in comparison to 1.185 volts/ms from a traditional 1st order sigma-delta. Findings have indicated that the proposed odd/even order sampling has superior SNR and sampling frequency performances, while the dynamic range is reduced by 8%.
Abstract-The proposed design of HDB3 decoding system using FPGA implementation offers an efficient and unfailing decoding at receiving end by sustaining clock data recovery using Direct Digital Synthesis (DDS). The system captures E1/T1 HDB3 encoded tertiary level stream at input, converts it into binary level symbols, FPGA IO reconcilable, and decode and transforms it into synchronized NRZ output. The receiver end of FPGA based HDB3 decoding system has never been implemented using clock data recovery. The resource efficient implementation and synthesis outcome illustrate that the design of HDB3 decoder is very simple and fault tolerant and its ASIC design can easily be surrogate by the proposed idea.Index Terms-AMI, clock data recovery, decoder, direct digital synthesis, E1, FPGA, HDB3, NRZ, T1
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.