66 MHz 2.3 M ternary dynamic content addressable memory

Lines, V.; Ahmed, Ali; Ma, Pan; Ma, Shenglin; McKenzie, Raymond J.; Kim, Hong-Seok; Mar, C.

doi:10.1109/mtdt.2000.868622

Cited by 29 publications

(12 citation statements)

References 2 publications

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“…Because of this there can be variations in the height and width of a cell and we leave these as optional parameters (the default height and width are extracted from [14]). For example, a Dynamic TCAM [16], [17] increases the effective number of bits per area because it uses only 1-transistor dynamic cell to store a bit. When our model is given the height and width of dynamic TCAM cell, we can estimate the power accurately even though the bit storage is completely different.…”

Section: Discussionmentioning

confidence: 99%

Ternary CAM Power and Delay Model: Extensions and Uses

Agrawal

Sherwood

2008

IEEE Trans. VLSI Syst.

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Abstract-Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search primitives on network processors and even custom application-specific integrated circuits (ASICs), achieving tight bounds on worst case performance with standard memories often requires a very careful analysis of all possible access patterns. An alternative, and often times more simple solution, is possible if a ternary CAM (TCAM) is used to perform a fully parallel search across the entire data set. Unfortunately, this parallelism means that large portions of the chip are switching during each cycle, causing large amounts of power to be consumed. While researchers at all levels of design (from algorithms to circuits) have begun to explore new ways of managing the power consumption, quantifying design alternatives is difficult due to a lack of available models. In this paper, we examine the structure of a modern TCAM and present a simple, yet accurate, power and delay model. We present techniques to estimate the dynamic power consumption and leakage power of a TCAM structure and validate the model using a combination of industrial TCAM datasheets and prior published works. Such a model is a critical first step in bridging the intellectual divide between circuit-level and algorithm-level optimizations. To demonstrate the utility of our model, we present an extensive analysis of the model by varying various architectural parameters and describe how our model can be easily extended to handle several circuit optimizations in the TCAM structure. In addition, we present a comparative study of SRAM and TCAM energy consumption to directly quantify the many design options which will be very useful for network designers to explore various power management schemes.

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Section: Discussionmentioning

confidence: 99%

Ternary CAM Power and Delay Model: Extensions and Uses

Agrawal

Sherwood

2008

IEEE Trans. VLSI Syst.

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“…Ternary CAMs are beginning to have acceptance as a viable alternatives for network processors [5,6,7]. This type of CAM is able to match in parallel stored data with incoming data, which in this case is a destination address.…”

Section: Ternary Content Addressable Memorymentioning

confidence: 99%

Associative ternary cache for IP routing

Rooney

Delgado-Frias

Summerville

2004

IEE Proc., Comput. Digit. Tech.

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Abstract. In this paper we present a study of a prefix routing cache for Internet IP routing. An output port assignment requires one cache memory access when the assignment is found in cache. The cache array is divided into sets that are of variable size; all entries within a set have the same prefix size. The cache is based on a ternary content addressable memory (TCAM) that matches 1, 0 and don't care (X) values. Our study shows that an associative ternary cache provides an output port at the speed of one memory access with a very high hit rate. For an 8K-entry cache the hit rate ranges from 97.62% to 99.67% on traces of 0.2 to 3.5 million addresses. A port error occurs when the port selected by the cache differs from the port that would have been selected from the routing table. In this paper we introduce a novel sampling technique that reduces the worst port error rate by an order of magnitude (from 0.52% to 0.05%).

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“…In this work, we focus on binary CAMs. Vol As a type of memory, CAM cells are manufactured using SRAM [7]- [12] or DRAM technology [13], [14]. While DRAM based CAMs provide larger capacities, SRAM based CAMs have seen higher adoption as they provide faster search speed, which is a priority for all applications using CAMs.…”

Section: Introductionmentioning

confidence: 99%

OE-CAM: A Hybrid Opto-Electronic Content Addressable Memory

et al. 2020

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A content addressable memory (CAM) is a type of memory that implements a parallel search engine at its core. A CAM takes as an input a value and outputs the address where this value is stored in case of a match. CAMs are used in a wide range of applications including networking, cashing, neuromorphic associative memories, multimedia, and data analytics. Here, we introduce a novel opto-electronic CAM (OE-CAM) utilizing the integrated silicon photonic platform. In our approach, we explore the performance of an experimental OE-CAM and verify the efficiency of the device at 25Gbit/s while maintaining the bit integrity under noise conditions. We show that OE-CAM enables a) two orders of magnitude faster search functionality resulting in b) a five orders of magnitude lower power-delay-product compared to CAMs implementations based on other emerging technologies. This remarkable performance potential is achieved by utilizing i) a high parallelism of wavelength-divisionmultiplexing in the optical domain, combined with ii) 10's of GHz-fast opto-electronic components, packaged in iii) integrated photonics for 10-100's ps-short communication delays. We further verify the upper optical input power limit of this OE-CAM to be given by parasitic nonlinearities inside the silicon waveguides, and the minimal detectable optical power at the back-end photoreceiver's responsivity given channel noise. Such energy-efficient and short-delay OE-CAMs could become a key component of functional photonic-augmented ASICS, co-processors, or smart sensors.

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66 MHz 2.3 M ternary dynamic content addressable memory

Cited by 29 publications

References 2 publications

Ternary CAM Power and Delay Model: Extensions and Uses

Ternary CAM Power and Delay Model: Extensions and Uses

Associative ternary cache for IP routing

OE-CAM: A Hybrid Opto-Electronic Content Addressable Memory

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