Alessio Santiccioli

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19Publications
74Citation Statements Received
61Citation Statements Given
How they've been cited
238
0
74
0
How they cite others
345
0
61
0
Publications
Order By: Most citations

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs

Avallone
1
,
Mercandelli
2
,
Santiccioli
3
et al. 2021
IEEE Trans. Circuits Syst. I
21
0
21
0
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Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops

Santiccioli
1
,
Samori
2
,
Lacaita
3
et al. 2019
IEEE Trans. Circuits Syst. I
13
0
14
0
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A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

Santiccioli
1
,
Mercandelli
2
,
Bertulessi
3
et al. 2020
IEEE J. Solid-State Circuits
44
0
12
0
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A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power

Santiccioli
1
,
Mercandelli
2
,
Lacaita
3
et al. 2019
8
0
8
0
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A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

Santiccioli
1
,
Mercandelli
2
,
Lacaita
3
et al. 2019
IEEE J. Solid-State Circuits
29
0
6
0
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17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter

Mercandelli
1
,
Santiccioli
2
,
Parisi
3
et al. 2020
30
0
5
0
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Power‐jitter trade‐off analysis in digital‐to‐time converters

Santiccioli
1
,
Samori
2
,
Lacaita
3
et al. 2017
Electron. lett.
18
0
3
0
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show abstract

17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking

Santiccioli
1
,
Mercandelli
2
,
Bertulessi
3
et al. 2020
7
0
2
0
View full textAdd to dashboardCite
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