Power‐jitter trade‐off analysis in digital‐to‐time converters

Santiccioli, Alessio; Samori, Carlo; Lacaita, A.L.; Levantino, Salvatore

doi:10.1049/el.2016.4577

Cited by 18 publications

(3 citation statements)

References 9 publications

(19 reference statements)

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“…The jitter variance J DTC,VS (unit is s 2 ) and power P DTC,VS (unit is mW) product of a VS DTC can be expressed as [45] where k is the Boltzmann constant, T is the temperature, t TOT,VS is the total delay of VS DTC, f REF is the reference frequency. The γ is the excessive noise factor, V DD is the supply voltage, V OV,N the over-drive voltage of NMOS transistor, and C is 4kT…”

Section: A Jitter-power Analysismentioning

confidence: 99%

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Liu

Zhang

Qiu

et al. 2021

IEEE Trans. Circuits Syst. I

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In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48 ps root-mean-square (RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than −59.0 dBc, and the reference spur is −64.5 dBc. The power consumptions are 1.85 mW and 1.22 mW, corresponding to figures of merit (FOM) of −240.4 dB and −245.5 dB.

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Section: A Jitter-power Analysismentioning

confidence: 99%

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Liu

Zhang

Qiu

et al. 2021

IEEE Trans. Circuits Syst. I

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“…Under the assumption that the reference path components (i.e. DTC and buffers) are CMOS-based, their jitter variance can be shown to be proportional to the reference clock frequency and inversely to the dissipated power [23]. This suggests the following figure-of-merit:…”

Section: Jitter-power Tradeoff Analysismentioning

confidence: 99%

“…The reference path, on the other hand, contains a DTC to operate the MDLL in fractional-N mode, which provides additional degrees of freedom to be leveraged. In fact, the analysis presented in [23] suggest two key guidelines to this regard:…”

Section: Jitter-power Tradeoff Analysismentioning

confidence: 99%

Inductorless Frequency Synthesizers for Low-Cost Wireless

Santiccioli

2021

Special Topics in Information Technology

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The quest for ubiquitous wireless connectivity, drives an increasing demand for compact and efficient means of frequency generation. Conventional synthesizer options, however, generally trade one requirement for the other, achieving either excellent levels of efficiency by leveraging LC-oscillators, or a very compact area by relying on ring-oscillators. This chapter describes a recently introduced class of inductorless frequency synthesizers, based on the periodic realignment of a ring-oscillator, that have the potential to break this tradeoff. After analyzing their jitter-power product, the conditions that ensure optimum performance are derived and a novel digital-to-time converter range-reduction technique is introduced, to enable low-jitter and low-power fractional-N frequency synthesis. A prototype, which implements the proposed design guidelines and techniques, has been fabricated in 65 nm CMOS. It occupies a core area of 0:0275 mm$$^{2}$$ 2 and covers the 1:6-to-3:0 GHz range, achieving an absolute rms jitter (integrated from 30 kHz-to-30 MHz) of 397 fs at 2:5 mW power. With a corresponding jitter-power figure-of-merit of −244 dB in the fractional-N mode, the prototype outperforms prior state-of-the-art inductorless frequency synthesizers.

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